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CY6264 Datasheet(PDF) 1 Page - Cypress Semiconductor

Part No. CY6264
Description  8K x 8 Static RAM
Download  9 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY6264 Datasheet(HTML) 1 Page - Cypress Semiconductor

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8K x 8 Static RAM
CY6264
Cypress Semiconductor Corporation
198 Champion Court
San Jose
, CA 95134-1709
408-943-2600
Document #: 001-02367 Rev. *A
Revised August 8, 2006
Features
• Temperature Ranges
— Commercial: 0°C to 70°C
— Industrial: –40°C to 85°C
— Automotive-A: –40°C to 85°C
• High Speed
— 55 ns
• CMOS for optimum speed/power
• Easy memory expansion with CE1, CE2 and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• Available in Pb-free and non Pb-free 28-lead SNC
package
Functional Description
The CY6264 is a high-performance CMOS static RAM
organized as 8192 words by 8 bits. Easy memory expansion
is provided by an active LOW chip enable (CE1), an active
HIGH chip enable (CE2), and active LOW output enable (OE)
and three-state drivers. Both devices have an automatic
power-down feature (CE1), reducing the power consumption
by over 70% when deselected. The CY6264 is packaged in a
450-mil (300-mil body) SOIC.
An active LOW write enable signal (WE) controls the
writing/reading operation of the memory. When CE1 and WE
inputs are both LOW and CE2 is HIGH, data on the eight data
input/output pins (I/O0 through I/O7) is written into the memory
location addressed by the address present on the address
pins (A0 through A12). Reading the device is accomplished by
selecting the device and enabling the outputs, CE1 and OE
active LOW, CE2 active HIGH, while WE remains inactive or
HIGH. Under these conditions, the contents of the location
addressed by the information on address pins is present on
the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH. A die coat is used to ensure alpha immunity.
Pin Configuration
A1
A2
A3
A4
A5
A6
A7
A8
I/O0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
CE2
A3
A2
A1
OE
A0
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
NC
A4
A5
A6
A7
A8
A9
A10
A11
A12
I/O0
I/O1
I/O2
GND
8K x 8
ARRAY
INPUT BUFFER
COLUMN DECODER
POWER
DOWN
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
CE1
CE2
WE
OE
Top View
SOIC
Logic Block Diagram


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