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PRELIMINARY
CY14E104L/CY14E104N
Document Number: 001-09603 Rev. *H
Page 8 of 22
AC Test Conditions
Input Pulse Levels ....................................................0V to 3V
Input Rise and Fall Times (10% - 90%) ........................ <5 ns
Input and Output Timing Reference Levels .................... 1.5V
Capacitance
In the following table, the capacitance parameters are listed.[10]
Parameter
Description
Test Conditions
Max
Unit
CIN
Input Capacitance
TA = 25°C, f = 1 MHz,
VCC = 0 to 3.0V
7pF
COUT
Output Capacitance
7
pF
Thermal Resistance
In the following table, the thermal resistance parameters are listed.[10]
Parameter
Description
Test Conditions
48-FBGA 44-TSOP II 54-TSOP II Unit
Θ
JA
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
28.82
31.11
30.73
°C/W
Θ
JC
Thermal Resistance
(Junction to Case)
7.84
5.56
6.08
°C/W
Figure 5. AC Test Loads
5.0V
OUTPUT
5 pF
R1
R2
512
Ω
5.0V
OUTPUT
30 pF
R1
R2
512
Ω
for tri-state specs
963
Ω
963
Ω
AC Switching Characteristics
Parameters
Description
15 ns
20 ns
25 ns
45 ns
Unit
Cypress
Parameters
Alt
Parameters
Min
Max
Min
Max
Min
Max
Min
Max
SRAM Read Cycle
tACE
tACS
Chip Enable Access Time
15
20
25
45
ns
tRC
[11]
tRC
Read Cycle Time
15
20
25
45
ns
tAA
[12]
tAA
Address Access Time
15
20
25
45
ns
tDOE
tOE
Output Enable to Data Valid
10
10
12
20
ns
tOHA
tOH
Output Hold After Address Change
3333
ns
tLZCE
[13]
tLZ
Chip Enable to Output Active
3333
ns
tHZCE
[13]
tHZ
Chip Disable to Output Inactive
7
8
10
15
ns
Notes
10. These parameters are guaranteed but not tested.
11. WE must be HIGH during SRAM read cycles.
12. Device is continuously selected with CE and OE both LOW.
13. Measured ±200 mV from steady state output voltage.
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