PRELIMINARY
CY14E104K/CY14E104M
Document #: 001-09604 Rev. *H
Page 4 of 28
Hardware STORE (HSB) Operation
The CY14E104K/CY14E104M provides the HSB pin to control
and acknowledge the STORE operations. The HSB pin is used
to request a hardware STORE cycle. When the HSB pin is driven
LOW, the CY14E104K/CY14E104M conditionally initiates a
STORE operation after tDELAY. An actual STORE cycle begins
only if a write to the SRAM has taken place since the last STORE
or RECALL cycle. The HSB pin also acts as an open drain driver
that is internally driven LOW to indicate a busy condition when
the STORE (initiated by any means) is in progress.
SRAM read and write operations that are in progress when HSB
is driven LOW by any means are given time to complete before
the STORE operation is initiated. After HSB goes LOW, the
CY14E104K/CY14E104M continues SRAM operations for
tDELAY. During tDELAY, multiple SRAM read operations may take
place. If a write is in progress when HSB is pulled LOW it is
allowed a time, tDELAY, to complete. However, any SRAM write
cycles requested after HSB goes LOW is inhibited until HSB
returns HIGH.
During any STORE operation, regardless of how it is initiated,
the CY14E104K/CY14E104M continues to drive the HSB pin
LOW, releasing it only when the STORE is complete. Upon
completion
of
the
STORE
operation
the
CY14E104K/CY14E104M remains disabled until the HSB pin
returns HIGH. Leave the HSB unconnected if it is not used.
Hardware RECALL (Power Up)
During power up, or after any low power condition (VCC <
VSWITCH), an internal RECALL request is latched. When VCC
again exceeds the sense voltage of VSWITCH, a RECALL cycle
is automatically initiated and takes tHRECALL to complete.
Software STORE
Data is transferred from the SRAM to the nonvolatile memory by
a software address sequence. The CY14E104K/CY14E104M
software STORE cycle is initiated by executing sequential CE
controlled read cycles from six specific address locations in
exact order. During the STORE cycle, an erase of the previous
nonvolatile data is first performed, followed by a program of the
nonvolatile elements. After a STORE cycle is initiated, further
input and output are disabled until the cycle is completed.
Because a sequence of reads from specific addresses is used
for STORE initiation, it is important that no other read or write
accesses intervene in the sequence, or the sequence is aborted
and no STORE or RECALL takes place.
To initiate the software STORE cycle, the following read
sequence must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8FC0 Initiate STORE cycle
The software sequence may be clocked with CE controlled reads
or OE controlled reads. After the sixth address in the sequence
is entered, the STORE cycle commences and the chip is
disabled. It is important to use read cycles and not write cycles
in the sequence, although it is not necessary that OE be LOW
for a valid sequence. After the tSTORE cycle time is fulfilled, the
SRAM is activated again for read and write operations.
Software RECALL
Data is transferred from the nonvolatile memory to the SRAM by
a software address sequence. A software RECALL cycle is
initiated with a sequence of read operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE controlled read operations must be
performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4C63 Initiate RECALL cycle
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared; then, the nonvolatile information is transferred into the
SRAM cells. After the tRECALL cycle time the SRAM is again
ready for read and write operations. The RECALL operation in
no way alters the data in the nonvolatile elements.
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