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ADVANCE
CY14E102L, CY14E102N
Document Number: 001-45755 Rev. *A
Page 11 of 21
Switching Waveforms
Figure 5. SRAM Read Cycle #1: Address Controlled[12, 13, 23]
Figure 6. SRAM Read Cycle #2: CE and OE Controlled[12, 23, 25]
tRC
tAA
tOHA
ADDRESS
DQ (DATA OUT)
DATA VALID
ADDRESS
tRC
CE
tACE
tLZCE
tPD
tHZCE
OE
tDOE
tLZOE
DATA VALID
ACTIVE
STANDBY
tPU
DQ (DATA OUT)
ICC
tLZBE
tDBE
tHZBE
HZOE
t
tHZCE
BHE , BLE
Notes
23. HSB must remain HIGH during READ and WRITE cycles.
24. CE or WE must be >VIH during address transitions.
25. BHE and BLE are applicable for x16 configuration only.
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