CY8C24123A
CY8C24223A, CY8C24423A
Document Number: 38-12028 Rev. *J
Page 10 of 55
28-Pin Part Pinout
Table 5. Pin Definitions - 28-Pin PDIP, SSOP, and SOIC
Pin
No.
Type
Pin
Name
Description
Figure 5. CY8C24423A 28-Pin PSoC Device
Digital Analog
1
I/O
I
P0[7]
Analog Column Mux Input
2
I/O
I/O
P0[5]
Analog Column Mux Input and column
output
3
I/O
I/O
P0[3]
Analog Column Mux Input and Column
Output
4
I/O
I
P0[1]
Analog Column Mux Input
5
I/O
P2[7]
6
I/O
P2[5]
7
I/O
I
P2[3]
Direct Switched Capacitor Block Input
8
I/O
I
P2[1]
Direct Switched Capacitor Block Input
9
Power
SMP
Switch Mode Pump (SMP) Connection to
External Components required
10
I/O
P1[7]
I2C Serial Clock (SCL)
11
I/O
P1[5]
I2C Serial Data (SDA)
12
I/O
P1[3]
13
I/O
P1[1]
Crystal Input (XTALin), I2C Serial Clock
(SCL), ISSP-SCLK*
14
Power
Vss
Ground connection.
15
I/O
P1[0]
Crystal Output (XTALout), I2C Serial Data
(SDA), ISSP-SDATA*
16
I/O
P1[2]
17
I/O
P1[4]
Optional External Clock Input (EXTCLK)
18
I/O
P1[6]
19
Input
XRES Active High External Reset with Internal
Pull Down
20
I/O
I
P2[0]
Direct Switched Capacitor Block Input
21
I/O
I
P2[2]
Direct Switched Capacitor Block Input
22
I/O
P2[4]
External Analog Ground (AGND)
23
I/O
P2[6]
External Voltage Reference (VRef)
24
I/O
I
P0[0]
Analog Column Mux Input
25
I/O
I
P0[2]
Analog Column Mux Input
26
I/O
I
P0[4]
Analog Column Mux Input
27
I/O
I
P0[6]
Analog Column Mux Input
28
Power
Vdd
Supply Voltage
LEGEND: A = Analog, I = Input, and O = Output.
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Pro-
grammable Sytem-on-Chip Technical Reference Manual for details.
A, I,P0[7]
A,IO, P0[5]
A,IO, P0[3]
A,I, P0[1]
P2[7]
P2[5]
A,I, P2[3]
A, I,P2[1]
SMP
I2CSCL,P1[7]
I2CSDA,P1[5]
P1[3]
I2CSCL,XTALin,P1[1]
Vss
Vdd
P0[6], A,I
P0[4], A,I
P0[2], A,I
P0[0], A,I
P2[6],ExternalVRef
P2[4],ExternalAGND
P2[2], A,I
P2[0], A,I
XRES
P1[6]
P1[4],EXTCLK
P1[2]
P1[0],XTALout,I2CSDA
PDIP
SSOP
SOIC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
[+] Feedback