CY14B101L
Document Number: 001-06400 Rev. *J
Page 2 of 18
Pinouts
Figure 1. Pin Diagram - 32-Pin SOIC and 48-Pin SSOP
Table 1. Pin Definitions
Pin Name
Alt
I/O Type
Description
A0–A16
Input
Address Inputs. Used to select one of the 131,072 bytes of the nvSRAM.
DQ0-DQ7
Input or Output Bidirectional Data IO Lines. Used as input or output lines depending on operation.
WE
W
Input
Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the IO
pins is written to the specific address location.
CE
E
Input
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
OE
G
Input
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during
read cycles. Deasserting OE HIGH causes the IO pins to tri-state.
VSS
Ground
Ground for the Device. The device is connected to ground of the system.
VCC
Power Supply
Power Supply Inputs to the Device.
HSB
Input or Output Hardware Store Busy (HSB). When LOW, this output indicates a Hardware Store is in progress.
When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak internal
pull up resistor keeps this pin high if not connected (connection optional).
VCAP
Power Supply
AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM
to nonvolatile elements.
NC
No Connect
No Connect. This pin is not connected to the die.
VCAP
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
VCC
A15
HSB
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
15
VSS
DQ2
DQ3
DQ4
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A16
NC
DQ7
DQ6
DQ5
NC
DQ4
VCC
DQ3
DQ2
DQ1
DQ0
VSS
A0
A1
A2
A3
A4
A5
A6
A7
NC
HSB
WE
NC
NC
A8
A9
A10
A11
A12
A13
A14
A15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Top View
(not to scale)
OE
CE
VCC
VSS
VCAP
NC
NC
NC
NC
NC
NC
NC
NC
NC
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