CY14B104K, CY14B104M

Document #: 001-07103 Rev. *S

Page 3 of 33

Pinouts

Figure 1. Pin Diagram - 44-PIn and 54-Pin TSOP II

Table 1. Pin Definitions

Pin Name

I/O Type

Description

Input

Address inputs. Used to select one of the 524,288 bytes of the nvSRAM for x8 configuration.

Address inputs. Used to select one of the 262,144 words of the nvSRAM for x16 configuration.

Bidirectional data I/O lines for ×16 configuration. Used as input or output lines depending on operation.

NC

No connect No connects. This pin is not connected to the die.

WE

Input

Write Enable input, Active LOW. When selected LOW, data on the I/O pins is written to the specific

address location.

CE

Input

Chip Enable input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.

OE

Input

Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read

cycles. Deasserting OE HIGH causes the I/O pins to tristate.

BHE

Input

BLE

Input

Output

Crystal connection. Drives crystal on startup.

Input

Crystal connection. For 32.768 kHz crystal.

NC

DQ5

DQ4

OE

CE

NC

NC

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

44 - TSOP II

Top View

(not to scale)

WE

HSB

INT

(x8)

NC

WE

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

54 - TSOP II

Top View

(not to scale)

OE

CE

INT

NC

NC

NC

54

53

52

51

49

50

HSB

BHE

BLE

(x16)

[4]

[4]

[5]

[5]

Notes

4. Address expansion for 8 Mbit. NC pin not connected to die.

5. Address expansion for 16 Mbit. NC pin not connected to die.

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