CY8C24094, CY8C24794
CY8C24894, CY8C24994
Document Number: 38-12018 Rev. *O
Page 2 of 47
2. PSoC Functional Overview
The
PSoC
family
consists
of
many
programmable
system-on-chips with On-Chip Controller devices. All PSoC
family devices are designed to replace traditional MCUs, system
ICs, and the numerous discrete components that surround them.
The PSoC CY8C24x94 devices are unique members of the
PSoC family because it includes a full featured, full speed (12
Mbps) USB port. Configurable analog, digital, and interconnect
circuitry enable a high level of integration in a host of industrial,
consumer, and communication applications.
This architecture enables the user to create customized
peripheral configurations that match the requirements of each
individual application. Additionally, a fast CPU, Flash program
memory, SRAM data memory, and configurable I/O are included
in a range of convenient pinouts and packages.
The PSoC architecture, as illustrated on the left, is comprised of
four main areas: PSoC Core, Digital System, Analog System,
and System Resources including a full speed USB port. Config-
urable global busing enables all the device resources to be
combined into a complete custom system. The PSoC
CY8C24x94 devices can have up to seven I/O ports that connect
to the global digital and analog interconnects, providing access
to 4 digital blocks and 6 analog blocks.
2.1 The PSoC Core
The PSoC Core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory, clocks, and configurable
GPI/O (General Purpose I/O).
The M8C CPU core is a powerful processor with speeds up to 24
MHz, providing a four MIPS 8-bit Harvard architecture micropro-
cessor. The CPU uses an interrupt controller with up to 20
vectors, to simplify programming of real time embedded events.
Program execution is timed and protected using the included
Sleep and Watch Dog Timers (WDT).
Memory encompasses 16K of Flash for program storage, 1K of
SRAM for data storage, and up to 2K of EEPROM emulated
using the Flash. Program Flash uses four protection levels on
blocks of 64 bytes, allowing customized software IP protection.
The PSoC device incorporates flexible internal clock generators,
including a 24 MHz IMO (internal main oscillator) accurate to 8%
over temperature and voltage. The 24 MHz IMO can also be
doubled to 48 MHz for use by the digital system. A low power 32
kHz ILO (internal low speed oscillator) is provided for the Sleep
timer and WDT. The clocks, together with programmable clock
dividers (as a System Resource), provide the flexibility to
integrate almost any timing requirement into the PSoC device. In
USB systems, the IMO self tunes to ± 0.25% accuracy for USB
communication.
PSoC GPIOs provide connection to the CPU, digital and analog
resources of the device. Each pin’s drive mode may be selected
from eight options, allowing great flexibility in external inter-
facing. Every pin is also capable of generating a system interrupt
on high level, low level, and change from last read.
2.2 The Digital System
The Digital System is composed of four digital PSoC blocks.
Each block is an 8-bit resource used alone or combined with
other blocks to form 8, 16, 24, and 32-bit peripherals, which are
called user module references.
Figure 2-1. Digital System Block Diagram
Digital peripheral configurations include the following:
■ Full Speed USB (12 Mbps)
■ PWMs (8 to 32 bit)
■ PWMs with Dead band (8 to 24 bit)
■ Counters (8 to 32 bit)
■ Timers (8 to 32 bit)
■ UART 8 bit with selectable parity
■ SPI master and slave
■ I2C slave and multi-master
■ Cyclical Redundancy Checker/Generator (8 to 32 bit)
■ IrDA
■ Pseudo Random Sequence Generators (8 to 32 bit)
The digital blocks are connected to any GPI/O through a series
of global buses that can route any signal to any pin. The buses
also enable signal multiplexing and performing logic operations.
This configurability frees the designs from the constraints of a
fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This enables you the
optimum choice of system resources for your application. Family
resources are shown in Table 2-1 on page 4.
DIGITAL SYSTEM
To System Bus
Digital Clocks
From Core
Digital PSoC Block Array
To Analog
System
8
8
8
8
Row 0
DBB00
DBB01
DCB02
DCB03
4
4
GIE[7:0]
GIO[7:0]
GOE[7:0]
GOO[7:0]
Global Digital
Interconnect
Port 1
Port 0
Port 3
Port 2
Port 5
Port 4
Port 7
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