10 / 36 page
CY8C21123, CY8C21223, CY8C21323
Document Number: 38-12022 Rev. *K
Page 10 of 36
24-Pin Part Pinout
Table 7. Pin Definitions - CY8C21323 24-Pin QFN[5]
Pin
No.
Type
Pin
Name
Description
Figure 7. CY8C21323 24-Pin QFN
Digital
Analog
1
IO
I
P0[1]
Analog Column Mux Input
2
Power
SMP
Switch Mode Pump (SMP) Connection to
required External Components
3
Power
Vss
Ground connection
4
IO
P1[7]
I2C Serial Clock (SCL)
5
IO
P1[5]
I2C Serial Data (SDA)
6
IO
P1[3]
7
IO
P1[1]
I2C Serial Clock (SCL), ISSP-SCLK[3]
8
NC
No Connection
9
Power
Vss
Ground Connection
10
IO
P1[0]
I2C Serial Data (SDA), ISSP-SDATA[3]
11
IO
P1[2]
12
IO
P1[4]
Optional External Clock Input (EXTCLK)
13
IO
P1[6]
14
Input
XRES
Active High External Reset with Internal
Pull Down
15
NC
No Connection
16
IO
I
P0[0]
Analog Column Mux Input
17
IO
I
P0[2]
Analog Column Mux Input
18
IO
I
P0[4]
Analog Column Mux Input
19
IO
I
P0[6]
Analog Column Mux Input
20
Power
Vdd
Supply Voltage
21
Power
Vss
Ground Connection
22
IO
I
P0[7]
Analog Column Mux Input
23
IO
I
P0[5]
Analog Column Mux Input
24
IO
I
P0[3]
Analog Column Mux Input
LEGEND A = Analog, I = Input, and O = Output.
QFN
(Top View)
A, I, P0[1]
SMP
Vss
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
1
2
3
4
5
6
18
17
16
15
14
13
P0[4], A, I
P0[2], A, I
NC
XRES
P1[6]
P0[0], A, I
Note
5. The center pad on the QFN package must be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it
must be electrically floated and not connected to any other signal.
[+] Feedback
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
