7 / 27 page  CY8C21345, CY8C22345, CY8C22545 Document Number: 001-43084 Rev. *H Page 7 of 27 Pinouts This PSoC device family is available in a variety of packages that are listed in the following tables. Every port pin (labeled with a “P”) is capable of Digital IO. However, Vss, Vdd, and XRES are not capable of Digital IO. CY8C22345, CY8C21345 28-Pin SOIC Table 3. Pin Definitions Pin No. Type Pin Name Description Digital Analog 1 IO I, MR P0[7] Integration Capacitor for MR 2 IO I, ML P0[5] Integration Capacitor for ML 3 IO I, ML P0[3] 4 IO I, ML P0[1] 5 IO I, ML P2[7] To Compare Column 0 6 IO ML P2[5] Optional ADC External Vref 7 IO ML P2[3] 8 IO ML P2[1] 9 Power Vss Ground Connection 10 IO ML P1[7] I2C Serial Clock (SCL) 11 IO ML P1[5] I2C Serial Data (SDA) 12 IO ML P1[3] 13 IO ML P1[1]* I2C Serial Clock (SCL), ISSP-SCLK 14 Power Vss Ground Connection 15 IO MR P1[0]* I2C Serial Clock (SCL), ISSP-SDATA 16 IO MR P1[2] 17 IO MR P1[4] Optional External Clock Input (EXT-CLK) 18 IO MR P1[6] 19 Input XRES Active High Pin Reset with Internal Pull Down 20 IO MR P2[0] 21 IO MR P2[2] 22 IO MR P2[4] 23 IO I, MR P2[6] To Compare Column 1 24 IO I, MR P0[0] 25 IO I, MR P0[2] 26 IO I, MR P0[4] 27 IO I, MR P0[6] 28 Power Vdd Supply Voltage LEGEND: A = Analog, I = Input, O = Output, M=Analog Mux input, MR= Analog Mux right input, ML= Analog Mux left input, * ISSP pin which is not HiZ at POR. AI, MR, P0[7] AI, ML, P0[5] AI, ML, P0[3] AI, ML, P0[1] AI, ML, P2[7] ADC_Ext_Vref, ML, P2[5] ML, P2[3] ML, P2[1] Vss I2C SCL, ML, P1[7] I2C SDA, ML, P1[5] ML, P1[3] I2C SCL, ML, P1[1] Vss Vdd P0[6], MR, AI P0[4], MR, AI P0[2], MR, AI P0[0], MR, AI P2[6], MR, AI P2[4], MR P2[2], MR P2[0], MR XRES P1[6], MR P1[4], MR, EXTCLK P1[2], MR P1[0], MR, I2C SDATA SOIC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Figure 3. Pin Diagram [+] Feedback |
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