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CY8C21123, CY8C21223, CY8C21323
Document Number: 38-12022 Rev. *K
Page 8 of 36
Table 5. Pin Definitions - CY8C21223 16-Pin COL [3]
Pin
No.
Type
Pin
Name
Description
Figure 5. CY8C21223 16-Pin COL
Digital
Analog
1
IO
I
P0[3]
Analog Column Mux Input
2
IO
I
P0[1]
Analog Column Mux Input
3
IO
P1[7]
I2C Serial Clock (SCL)
4
IO
P1[5]
I2C Serial Data (SDA)
5
IO
P1[3]
6
IO
P1[1]
I2C Serial Clock (SCL), ISSP-SCLK[3]
7
Power
Vss
Ground Connection
8
IO
P1[0]
I2C Serial Data (SDA), ISSP-SDATA[3]
9
IO
P1[6]
10
IO
P1[4]
EXTCLK
11
Input
XRES
Active High External Reset with Internal
Pull Down
12
IO
I
P0[4]
VREF
13
Power
Vdd
Supply Voltage
14
IO
I
P0[7]
Analog Column Mux Input
15
IO
I
P0[5]
Analog Column Mux Input
16
NC
No Connect
LEGEND A = Analog, I = Input, and O = Output.
COL
(Top View)
1
2
3
4
12
11
10
9
P0[4], VREF
XRES
P1[4]
P1[6]
AI, P0[3]
AI, P0[1]
I2C SCL, P1[7]
I2C SDA, P1[5]
Notes
3. These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable System-on-Chip Technical Reference Manual for details.
4. The center pad on the QFN package must be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it
must be electrically floated and not connected to any other signal.
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