PRELIMINARY
CY7C1566KV18, CY7C1577KV18
CY7C1568KV18, CY7C1570KV18
72-Mbit DDR-II+ SRAM 2-Word Burst
Architecture (2.5 Cycle Read Latency)
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
, CA 95134-1709
•
408-943-2600
Document Number: 001-15880 Rev. *D
Revised April 24, 2009
Features
■ 72 Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36)
■ 550 MHz clock for high bandwidth
■ 2-word burst for reducing address bus frequency
■ Double Data Rate (DDR) interfaces
(data transferred at 1100 MHz) at 550 MHz
■ Available in 2.5 clock cycle latency
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
■ Data valid pin (QVLD) to indicate valid data on the output
■ Synchronous internally self-timed writes
■ DDR-II+ operates with 2.5 cycle read latency when DOFF is
asserted HIGH
■ Operates similar to DDR-I device with 1 cycle read latency
when DOFF is asserted LOW
■ Core VDD = 1.8V ± 0.1V; IO VDDQ = 1.4V to VDD
[1]
❐ Supports both 1.5V and 1.8V IO supply
■ HSTL inputs and variable drive HSTL output buffers
■ Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)
■ Offered in both Pb-free and non Pb-free packages
■ JTAG 1149.1 compatible test access port
■ Phase-Locked Loop (PLL) for accurate data placement
Configurations
With Read Cycle Latency of 2.5 cycles:
CY7C1566KV18 – 8M x 8
CY7C1577KV18 – 8M x 9
CY7C1568KV18 – 4M x 18
CY7C1570KV18 – 2M x 36
Functional Description
The CY7C1566KV18, CY7C1577KV18, CY7C1568KV18, and
CY7C1570KV18 are 1.8V Synchronous Pipelined SRAMs
equipped with DDR-II+ architecture. The DDR-II+ consists of an
SRAM core with advanced synchronous peripheral circuitry.
Addresses for read and write are latched on alternate rising
edges of the input (K) clock. Write data is registered on the rising
edges of both K and K. Read data is driven on the rising edges
of K and K. Each address location is associated with two 8-bit
words (CY7C1566KV18), 9-bit words (CY7C1577KV18), 18-bit
words (CY7C1568KV18), or 36-bit words (CY7C1570KV18) that
burst sequentially into or out of the device.
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs D) are tightly matched to the two
output echo clocks CQ/CQ, eliminating the need for separately
capturing data from each individual DDR SRAM in the system
design.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
Table 1. Selection Guide
Description
550 MHz
500 MHz
450 MHz
400 MHz
Unit
Maximum Operating Frequency
550
500
450
400
MHz
Maximum Operating Current
x8
740
690
630
580
mA
x9
740
690
630
580
x18
760
700
650
590
x36
970
890
820
750
Note
1. The Cypress QDR-II+ devices surpass the QDR consortium specification and can support VDDQ = 1.4V to VDD.
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