Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.COM

X  

CY7C1411AV18-167BZXC Datasheet(PDF) 9 Page - Cypress Semiconductor

Part # CY7C1411AV18-167BZXC
Description  36-Mbit QDR-II SRAM 4-Word Burst Architecture
Download  31 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1411AV18-167BZXC Datasheet(HTML) 9 Page - Cypress Semiconductor

Back Button CY7C1411AV18-167BZXC Datasheet HTML 5Page - Cypress Semiconductor CY7C1411AV18-167BZXC Datasheet HTML 6Page - Cypress Semiconductor CY7C1411AV18-167BZXC Datasheet HTML 7Page - Cypress Semiconductor CY7C1411AV18-167BZXC Datasheet HTML 8Page - Cypress Semiconductor CY7C1411AV18-167BZXC Datasheet HTML 9Page - Cypress Semiconductor CY7C1411AV18-167BZXC Datasheet HTML 10Page - Cypress Semiconductor CY7C1411AV18-167BZXC Datasheet HTML 11Page - Cypress Semiconductor CY7C1411AV18-167BZXC Datasheet HTML 12Page - Cypress Semiconductor CY7C1411AV18-167BZXC Datasheet HTML 13Page - Cypress Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 9 / 31 page
background image
CY7C1411AV18, CY7C1426AV18
CY7C1413AV18, CY7C1415AV18
Document Number: 38-05614 Rev. *D
Page 9 of 31
previous state of the SRAM. If both ports were deselected, the
read port takes priority. If a read was initiated on the previous
cycle, the write port takes priority (as read operations can not be
initiated on consecutive cycles). If a write was initiated on the
previous cycle, the read port takes priority (as write operations
can not be initiated on consecutive cycles). Therefore, asserting
both port selects active from a deselected state results in alter-
nating read or write operations being initiated, with the first
access being a read.
Depth Expansion
The CY7C1413AV18 has a port select input for each port. This
enables for easy depth expansion. Both port selects are sampled
on the rising edge of the positive input clock only (K). Each port
select input can deselect the specified port. Deselecting a port
does not affect the other port. All pending transactions (read and
write) completes prior to the device being deselected.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and VSS to allow the SRAM to adjust its output
driver impedance. The value of RQ must be 5X the value of the
intended line impedance driven by the SRAM. The allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15% is between 175
Ω and 350Ω, with V
DDQ =1.5V. The
output impedance is adjusted every 1024 cycles upon power up
to account for drifts in supply voltage and temperature.
Echo Clocks
Echo clocks are provided on the QDR-II to simplify data capture
on high-speed systems. Two echo clocks are generated by the
QDR-II. CQ is referenced with respect to C and CQ is referenced
with respect to C. These are free running clocks and are synchro-
nized to the output clock of the QDR-II. In the single clock mode,
CQ is generated with respect to K and CQ is generated with
respect to K. The timings for the echo clocks are shown in the
Switching Characteristics on page 23.
DLL
These chips use a Delay Lock Loop (DLL) that is designed to
function between 120 MHz and the specified maximum clock
frequency. During power up, when the DOFF is tied HIGH, the
DLL gets locked after 1024 cycles of stable clock. The DLL can
also be reset by slowing or stopping the input clock K and K for
a minimum of 30 ns. However, it is not necessary to reset the
DLL to lock to the desired frequency. The DLL automatically
locks 1024 clock cycles after a stable clock is presented. The
DLL may be disabled by applying ground to the DOFF pin. For
information refer to the application note AN5062, DLL Consider-
ations in QDRII/DDRII/QDRII+/DDRII+.
Application Example
Figure 1 shows four QDR-II used in an application.
Figure 1. Application Example
R = 250
ohms
Vt
R
R = 250
ohms
Vt
Vt
R
Vt = Vddq/2
R = 50
ohms
R
CC#
D
A
SRAM #4
R
P
S
#
W
P
S
#
B
W
S
#
K
ZQ
CQ/CQ#
Q
K#
CC#
D
A
K
SRAM #1
R
P
S
#
W
P
S
#
B
W
S
#
ZQ
CQ/CQ#
Q
K#
BUS
MASTER
(CPU
or
ASIC)
DATA IN
DATA OUT
Address
RPS#
WPS#
BWS#
Source K
Source K#
Delayed K
Delayed K#
CLKIN/CLKIN#
[+] Feedback


Similar Part No. - CY7C1411AV18-167BZXC

ManufacturerPart #DatasheetDescription
logo
Cypress Semiconductor
CY7C1411AV18-167BZXC CYPRESS-CY7C1411AV18-167BZXC Datasheet
1Mb / 28P
   36-Mbit QDR??II SRAM 4-Word Burst Architecture
More results

Similar Description - CY7C1411AV18-167BZXC

ManufacturerPart #DatasheetDescription
logo
Cypress Semiconductor
CY7C1411BV18 CYPRESS-CY7C1411BV18 Datasheet
1Mb / 28P
   36-Mbit QDR??II SRAM 4-Word Burst Architecture
CY7C1411BV18_0709 CYPRESS-CY7C1411BV18_0709 Datasheet
705Kb / 30P
   36-Mbit QDR??II SRAM 4-Word Burst Architecture
CY7C1411JV18 CYPRESS-CY7C1411JV18_09 Datasheet
698Kb / 28P
   36-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1411BV18 CYPRESS-CY7C1411BV18_09 Datasheet
732Kb / 30P
   36-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1411AV18 CYPRESS-CY7C1411AV18 Datasheet
1Mb / 28P
   36-Mbit QDR??II SRAM 4-Word Burst Architecture
CY7C1411JV18 CYPRESS-CY7C1411JV18 Datasheet
644Kb / 26P
   36-Mbit QDR??II SRAM 4-Word Burst Architecture
CY7C1410AV18 CYPRESS-CY7C1410AV18 Datasheet
277Kb / 23P
   36-Mbit QDR-II??SRAM 2-Word Burst Architecture
CY7C1410AV18 CYPRESS-CY7C1410AV18_07 Datasheet
1Mb / 25P
   36-Mbit QDR-II??SRAM 2-Word Burst Architecture
CY7C1410BV18 CYPRESS-CY7C1410BV18 Datasheet
1Mb / 26P
   36-Mbit QDR-II??SRAM 2-Word Burst Architecture
CY7C1410JV18 CYPRESS-CY7C1410JV18 Datasheet
629Kb / 26P
   36-Mbit QDR??II SRAM 2-Word Burst Architecture
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com