PRELIMINARY
CY7C1566KV18, CY7C1577KV18
CY7C1568KV18, CY7C1570KV18
Document Number: 001-15880 Rev. *D
Page 9 of 28
Valid Data Indicator (QVLD)
QVLD is provided on the DDR-II+ to simplify data capture on high
speed systems. The QVLD is generated by the DDR-II+ device
along with data output. This signal is also edge aligned with the
echo clock and follows the timing of any data pin. This signal is
asserted half a cycle before valid data arrives.
PLL
These chips use a PLL that is designed to function between 120
MHz and the specified maximum clock frequency. During power
up, when the DOFF is tied HIGH, the PLL is locked after 20
μs
of stable clock. The PLL can also be reset by slowing or stopping
the input clock K and K for a minimum of 30 ns. However, it is
not necessary to reset the PLL to lock to the desired frequency.
The PLL automatically locks 20
μs after a stable clock is
presented. The PLL may be disabled by applying ground to the
DOFF pin. When the PLL is turned off, the device behaves in
DDR-I mode (with one cycle latency and a longer access time).
For information, refer to the application note, PLL Considerations
in QDRII/DDRII/QDRII+/DDRII+.
Application Example
Figure 1 shows two DDR-II+ used in an application.
Figure 1. Application Example
DQ
A
SRAM#2
LD
CQ/CQ
K
ZQ
K
R/W BWS
BUS
MASTER
(CPU or ASIC)
DQ
Addresses
LD
R/W
R = 250ohms
Source CLK
Source CLK
Echo Clock1/Echo Clock1
Echo Clock2/Echo Clock2
R = 250ohms
BWS
DQ
A
SRAM#1
LD
K
ZQ
CQ/CQ
K
R/W BWS
[+] Feedback