CY7C68001
Document #: 38-08013 Rev. *J
Page 9 of 45
To send more than 64 bytes, the process is repeated. The SX2
internally stores the length of the data phase that was specified
in the wLength field (bytes 6,7) of the setup packet. To send less
than the requested amount of data, the external master writes a
packet that is less than 64 bytes, or if a multiple of 64, the
external master follows the data with a zero-length packet. When
the SX2 sees a short or zero-length packet, it completes the
setup transfer by automatically completing the handshake
phase. The SX2 does not enable more data than the wLength
field specified in the setup packet. Note: the PKTEND pin does
not apply to Endpoint 0. The only way to send a short or zero
length packet is by writing to the byte count register with the
appropriate value.
For an OUT setup transaction, the external master can read
each packet received from the USB host during the data phase.
The steps to read a packet are as follows:
1. Wait for an EP0BUF interrupt, indicating that a packet was
received from the USB host into the buffer.
2. Initiate a read request for the byte count register, 0x33. This
indicates the amount of data received from the host.
3. Initiate a read request for register 0x31.
4. Read one byte.
5. Repeat steps 3 and 4 until the number of bytes specified in
the byte count register has been read.
To receive more than 64 bytes, the process is repeated. The SX2
internally stores the length of the data phase that was specified
in the wLength field of the setup packet (bytes 6,7). When the
SX2 sees that the specified number of bytes have been received,
it completes the set up transfer by automatically completing the
handshake phase. If the external master does not wish to receive
the entire transfer, it can stall the transfer.
If the SX2 receives another setup packet before the current
transfer has completed, it interrupts the external master with
another SETUP interrupt. If the SX2 receives a setup packet with
no data phase, the external master can accept the packet and
complete the handshake phase by writing zero to the byte count
register.
The SX2 automatically responds to all USB standard requests
covered in chapter 9 of the USB 2.0 specification except the
Set/Clear Feature Endpoint requests. When the host issues a
Set Feature or a Clear feature request, the SX2 triggers a
SETUP interrupt to the external master. The USB spec requires
that the device respond to the Set endpoint feature request by
doing the following:
■ Set the STALL condition on that endpoint.
The USB spec requires that the device respond to the Clear
endpoint feature request by doing the following:
■ Reset the Data Toggle for that endpoint
■ Clear the STALL condition of that endpoint.
The register that is used to reset the data toggle TOGCTL
(located at XDATA location 0xE683) is not an index register that
can be addressed by the command protocol presented in
Command Protocol on page 7. The following section provides
further information on this register bits and how to reset the data
toggle accordingly using a different set of command protocol
sequence.
7.1 Resetting Data Toggle
Table 7-1. Bit definition of the TOGCTL register
Bit 7: Q, Data Toggle Value
Q=0 indicates DATA0 and Q=1 indicates DATA1, for the endpoint
selected by the I/O and EP3:0 bits. Write the endpoint select bits
(IO and EP3:0), before reading this value.
Bit 6: S, Set Data Toggle to DATA1
After selecting the desired endpoint by writing the endpoint select
bits (IO and EP3:0), set S=1 to set the data toggle to DATA1. The
endpoint selection bits should not be changed while this bit is
written.
Bit 5: R, Set Data Toggle to DATA0
Set R=1 to set the data toggle to DATA0. The endpoint selection
bits should not be changed while this bit is written.
Bit 4: IO, Select IN or OUT Endpoint
Set this bit to select an endpoint direction prior to setting its R or
S bit. IO=0 selects an OUT endpoint, IO = 1 selects an IN
endpoint.
Bit 3-0: EP3:0, Select Endpoint
Set these bits to select an endpoint prior to setting its R or S bit.
Valid values are 0, 1, 2, 6, and 8.
TOGCTL
0xE683
Bit #
7
6
5
4
3
2
1
0
Bit Name
Q
S
R
I/O
EP3
EP2
EP1
EP0
Read/Write
R
W
W
R/W
R/W
R/W
R/W
R/W
Default
00
1
1
0
0
1
0
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