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CY7C1522JV18, CY7C1529JV18
CY7C1523JV18, CY7C1524JV18
Document #: 001-44700 Rev. *B
Page 3 of 27
Logic Block Diagram (CY7C1523JV18)
Logic Block Diagram (CY7C1524JV18)
CLK
A(20:0)
Gen.
K
K
Control
Logic
Address
Register
D[17:0]
Read Data Reg.
LD
Q[17:0]
Reg.
Reg.
Reg.
18
36
18
BWS[1:0]
VREF
Write
Data Reg
18
18
21
18
R/W
LD
R/W
CQ
CQ
DOFF
Write
Data Reg
Control
Logic
C
C
18
CLK
A(19:0)
Gen.
K
K
Control
Logic
Address
Register
D[35:0]
Read Data Reg.
LD
Q[35:0]
Reg.
Reg.
Reg.
36
72
36
BWS[3:0]
VREF
Write
Data Reg
36
36
20
36
R/W
LD
R/W
CQ
CQ
DOFF
Write
Data Reg
Control
Logic
C
C
36
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