10 / 30 page
CY7C603xx
Document #: 38-16018 Rev. *F
Page 10 of 30
Register Reference
This section lists the registers of the enCoRe III LV device. For
detailed register information, refer the PSoC System-on-Chip
Technical Reference Manual.
Register Conventions
The register conventions specific to this section are listed in
Table 5.
Register Mapping Tables
The enCoRe III LV device has a total register address space of
512 bytes. The register space is referred to as IO space and is
divided into two banks. The XOI bit in the Flag register (CPU_F)
determines which bank the user is currently in. When the XOI bit
is set the user is in Bank 1.
Note In the following register mapping tables, blank fields are
Reserved and must not be accessed.
Table 5. Register Conventions
Convention
Description
R
Read register or bit(s)
W
Write register or bit(s)
L
Logical register or bit(s)
C
Clearable register or bit(s)
#
Access is bit specific
Table 6. Register Map 0 Table: User Space
Name
Addr
(0,Hex) Access
Name
Addr
(0,Hex)
Access
Name
Addr
(0,Hex)
Access
Name
Addr
(0,Hex)
Access
PRT0DR
00
RW
40
ASE10CR0
80
RW
C0
PRT0IE
01
RW
41
81
C1
PRT0GS
02
RW
42
82
C2
PRT0DM2
03
RW
43
83
C3
PRT1DR
04
RW
44
ASE11CR0
84
RW
C4
PRT1IE
05
RW
45
85
C5
PRT1GS
06
RW
46
86
C6
PRT1DM2
07
RW
47
87
C7
PRT2DR
08
RW
48
88
C8
PRT2IE
09
RW
49
89
C9
PRT2GS
0A
RW
4A
8A
CA
PRT2DM2
0B
RW
4B
8B
CB
PRT3DR
0C
RW
4C
8C
CC
PRT3IE
0D
RW
4D
8D
CD
PRT3GS
0E
RW
4E
8E
CE
PRT3DM2
0F
RW
4F
8F
CF
10
50
90
CUR_PP
D0
RW
11
51
91
STK_PP
D1
RW
12
52
92
D2
13
53
93
IDX_PP
D3
RW
14
54
94
MVR_PP
D4
RW
15
55
95
MVW_PP
D5
RW
16
56
96
I2C_CFG
D6
RW
17
57
97
I2C_SCR
D7
#
18
58
98
I2C_DR
D8
RW
19
59
99
I2C_MSCR
D9
#
1A
5A
9A
INT_CLR0
DA
RW
1B
5B
9B
INT_CLR1
DB
RW
1C
5C
9C
DC
Blank fields are Reserved and must not be accessed.
# Access is bit specific.
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