CY7C4255, CY7C4265, CY7C4265A
Document #: 38-06004 Rev. *E
Page 3 of 23
Table 3. Pin Definitions
Signal Name
Description
I/O
Function
D0 –17
Data Inputs
I
Data inputs for an 18-bit bus.
Q0–17
Data Outputs
O Data outputs for an 18-bit bus.
WEN
Write Enable
I
Enables the WCLK input.
REN
Read Enable
I
Enables the RCLK input.
WCLK
Write Clock
I
The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not Full.
When LD is asserted, WCLK writes data into the programmable flag-offset register.
RCLK
Read Clock
I
The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is not
Empty. When LD is asserted, RCLK reads data out of the programmable flag-offset
register.
WXO/HF
Write Expansion
Out/Half Full Flag
O Dual-Mode Pin:
Single device or width expansion – Half Full status flag.
Cascaded – Write Expansion Out signal, connected to WXI of next device.
EF
Empty Flag
O When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
FF
Full Flag
O When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
PAE
Programmable
Almost Empty
O When PAE is LOW, the FIFO is almost empty based on the almost-empty offset value
programmed into the FIFO. PAE is asynchronous when VCC/SMODE is tied to VCC; it
is synchronized to RCLK when VCC/SMODE is tied to VSS.
PAF
Programmable
Almost Full
O When PAF is LOW, the FIFO is almost full based on the almost full offset value
programmed into the FIFO. PAF is asynchronous when VCC/SMODE is tied to VCC; it
is synchronized to WCLK when VCC/SMODE is tied to VSS.
LD
Load
I
When LD is LOW, D0–17 (Q0–17) are written (read) into (from) the program-
mable-flag-offset register.
FL/RT
First Load/
Retransmit
I
Dual-Mode Pin:
Cascaded – The first device in the daisy chain has FL tied to VSS; all other devices
has FL tied to VCC. In standard mode or width expansion, FL is tied to VSS on all
devices.
Not Cascaded – Tied to VSS. Retransmit function is also available in stand-alone mode
by strobing RT.
WXI
Write Expansion
Input
I
Cascaded – Connected to WXO of previous device.
Not Cascaded – Tied to VSS.
RXI
Read Expansion
Input
I
Cascaded – Connected to RXO of previous device.
Not Cascaded – Tied to VSS.
RXO
Read Expansion
Output
O Cascaded – Connected to RXI of next device.
RS
Reset
I
Resets device to empty condition. A reset is required before an initial read or write
operation after power up.
OE
Output Enable
I
When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected.
If OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.
VCC/SMODE Synchronous
Almost Empty/
Almost Full Flags
I
Dual-Mode Pin:
Asynchronous Almost Empty/Almost Full flags – tied to VCC.
Synchronous Almost Empty/Almost Full flags – tied to VSS.
(Almost Empty synchronized to RCLK, Almost Full synchronized to WCLK.)
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