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UCC1806 Datasheet(PDF) 5 Page - Texas Instruments

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Part No. UCC1806
Description  Low Power, Dual Output, Current Mode PWM Controller
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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UCC1806 Datasheet(HTML) 5 Page - Texas Instruments

   
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5
UCC1806
UCC2806
UCC3806
VREF to ground. To calculate the current limit adjust volt-
age threshold the following equations can be used;
Current Limit Adjust Latching Mode Voltage:
V
VR
A
R
R
mV
REF
=
+
>
–(
)
1 300
1
1
2
350
µ
Current Limit Adjust Non-Latching Mode Voltage:
V
VR
A
R
R
mV
REF
=
+
>
–(
)
180
1
1
2
350
µ
where R1 is the resistance from the VREF to CURLIM
and R2 is the resistance from CURLIM to GND.
GND: GND is the reference ground and power ground for
all functions of this part. Bypass and timing capacitors
should be connected as close as possible to GND.
INV: INV is the inverting input of the error amplifier and
has a common mode range from 0V to VIN –2V.
NI: NI is the non-inverting input of the error amplifier and
has a common mode range from 0V to VIN –2V.
RT: RT is the connection point for the oscillator timing re-
sistor. It has a low impedance input and is nominally at
1.25V. The current through RT is mirrored to the timing
capacitor pin, CT. This causes a linear charging of CT
from 0V to 2.35V. Note that the current mirror is limited to
a maximum of 100
µA so RT must be greater than 12.5k.
SHUTDOWN: The SHUTDOWN pin is provided for en-
hanced protection. When SHUTDOWN is driven above
1V, AOUT and BOUT are forced low.
SYNC: SYNC is a bi-directional pin, allowing or providing
external synchronization with TTL compatible thresholds.
In a typical application RT is connected through a timing
resistor to GND which allows the internal oscillator to
free run. In this mode SYNC outputs a TTL compatible
pulse during the oscillator dead time (when CT is being
discharged). If RT is forced above 4.4V, SYNC acts as an
input with TTL compatible thresholds and the internal os-
cillator is disabled. When SYNC is high, greater than 2V
the outputs are held active low. When SYNC returns low,
the outputs may be high until the on-time is terminated
by the normal peak current signal, a fault seen at SHUT-
DOWN or the next high assertion of SYNC. Multiple
UCC3806s can be synchronized by a single master
UCC3806 or external clock.
VC: VC is the input supply connection for the FET drive
outputs and has an input range of 2.5V to 15V. VC
should be capacitively bypassed for proper operation.
VIN: VIN is the input supply connection for this device.
The UCC1806 has a maximum startup threshold of 8V
and internally limited by means of a 15V shunt regulator.
The shunted supply current must be limited to 2.5mA.
For proper operation, VIN must be bypassed to GND with
at least a 0.01
µF ceramic capacitor.
VREF: VREF is a 5.1V ±1% trimmed reference output with
a 5mA maximum available current. VREF must be by-
passed to GND with at least a 0.1
µF ceramic capacitor
for proper operation.
PIN DESCRIPTIONS (continued)
40
42
44
46
48
50
52
54
56
58
60
-55 -50
-25
0
25
50
75
100
125
Temperature (°C)
Figure 2. Oscillator frequency vs. temperature.
-20
0
20
40
60
80
1k
10k
100k
1M
Frequency (Hz)
10M
0
45
90
135
Figure 1. Error amplifier gain and phase response.
TYPICAL CHARACTERISTICS


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