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PRELIMINARY
CY7C1566KV18, CY7C1577KV18
CY7C1568KV18, CY7C1570KV18
Document Number: 001-15880 Rev. *D
Page 2 of 28
Logic Block Diagram (CY7C1566KV18)
Logic Block Diagram (CY7C1577KV18)
Write
Reg
Write
Reg
CLK
A(21:0)
Gen.
K
K
Control
Logic
Address
Register
Read Data Reg.
R/W
Output
Logic
Reg.
Reg.
Reg.
8
16
8
NWS[1:0]
VREF
8
22
8
LD
Control
R/W
DOFF
8
DQ[7:0]
8
CQ
CQ
QVLD
Write
Reg
Write
Reg
CLK
A(21:0)
Gen.
K
K
Control
Logic
Address
Register
Read Data Reg.
R/W
Output
Logic
Reg.
Reg.
Reg.
9
18
9
BWS[0]
VREF
9
22
9
LD
Control
R/W
DOFF
9
DQ[8:0]
9
CQ
CQ
QVLD
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