9

FN6881.0

March 19, 2009

Timing Diagram

Operation and Adaptive Shoot-Through Protection

Designed for high speed switching, the ISL6611A MOSFET

driver controls two-phase power trains’ high-side and low-side

N-Channel FETs from one externally provided PWM signal.

A rising transition on PWM initiates the turn-off of the lower

MOSFET (see Figure 1). After a short propagation delay

are provided in the “Electrical Specifications” on page 8.

Adaptive shoot-through circuitry monitors the LGATE voltage

and turns on the upper gate following a short delay time

MOSFET turns on.

A falling transition on PWM indicates the turn-off of the upper

MOSFET and the turn-on of the lower MOSFET. The upper

which is modulated by the current balance circuits. The

adaptive shoot-through circuitry monitors the UGATE-PHASE

voltage and turns on the lower MOSFET a short delay time,

MOSFET. These methods prevent both the lower and upper

MOSFETs from conducting simultaneously (shoot-through),

while adapting the dead time to the gate charge

characteristics of the MOSFETs being used.

This driver is optimized for voltage regulators with large step

down ratio. The lower MOSFET is usually sized larger

compared to the upper MOSFET because the lower

MOSFET conducts for a longer time during a switching

period. The lower gate driver is therefore sized much larger

to meet this application requirement. The 0.4

Ω

ON-resistance and 4A sink current capability enable the

lower gate driver to absorb the current injected into the lower

MOSFET and help prevent shoot through caused by the self

turn-on of the lower MOSFET due to high dV/dt of the

switching node.

Tri-State PWM Input

A unique feature of the ISL6611A is the adaptable tri-state

PWM input. Once the PWM signal enters the shutdown

window, either MOSFET previously conducting is turned off.

If the PWM signal remains within the shutdown window for

longer than 25ns of the previously conducting MOSFET, the

output drivers are disabled and both MOSFET gates are

pulled and held low. The shutdown state is removed when

the PWM signal moves outside the shutdown window. The

PWM Tri-state rising and falling thresholds outlined in the

“Electrical Specifications” on page 8 determine when the

lower and upper gates are enabled. During normal operation

in a typical application, the PWM rise and fall times through

the shutdown window should not exceed either output’s turn-

off propagation delay plus the MOSFET gate discharge time

to ~1V. Abnormally long PWM signal transition times through

the shutdown window will simply introduce additional dead

time between turn off and turn on of the synchronous

bridge’s MOSFETs. For optimal performance, no more than

100pF parasitic capacitive load should be present on the

PWM line of ISL6611A (assuming an Intersil PWM controller

is used).

Bootstrap Considerations

This driver features an internal bootstrap diode. Simply

adding an external capacitor across the BOOT and PHASE

PWM

UGATE

LGATE

1V

2.5V

1V

FIGURE 1. TIMING DIAGRAM

ISL6611A