Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.COM

X  

CY7C1511JV18-300BZXC Datasheet(PDF) 6 Page - Cypress Semiconductor

Part # CY7C1511JV18-300BZXC
Description  72-Mbit QDR-II SRAM 4-Word Burst Architecture
Download  29 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1511JV18-300BZXC Datasheet(HTML) 6 Page - Cypress Semiconductor

Back Button CY7C1511JV18-300BZXC Datasheet HTML 2Page - Cypress Semiconductor CY7C1511JV18-300BZXC Datasheet HTML 3Page - Cypress Semiconductor CY7C1511JV18-300BZXC Datasheet HTML 4Page - Cypress Semiconductor CY7C1511JV18-300BZXC Datasheet HTML 5Page - Cypress Semiconductor CY7C1511JV18-300BZXC Datasheet HTML 6Page - Cypress Semiconductor CY7C1511JV18-300BZXC Datasheet HTML 7Page - Cypress Semiconductor CY7C1511JV18-300BZXC Datasheet HTML 8Page - Cypress Semiconductor CY7C1511JV18-300BZXC Datasheet HTML 9Page - Cypress Semiconductor CY7C1511JV18-300BZXC Datasheet HTML 10Page - Cypress Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 6 / 29 page
background image
CY7C1511JV18, CY7C1526JV18
CY7C1513JV18, CY7C1515JV18
Document Number: 001-12560 Rev. *E
Page 6 of 29
Pin Definitions
Pin Name
IO
Pin Description
D[x:0]
Input-
Synchronous
Data Input Signals. Sampled on the rising edge of K and K clocks when valid write operations are active.
CY7C1511JV18
− D
[7:0]
CY7C1526JV18
− D
[8:0]
CY7C1513JV18
− D
[17:0]
CY7C1515JV18
− D
[35:0]
WPS
Input-
Synchronous
Write Port Select
− Active LOW. Sampled on the rising edge of the K clock. When asserted active, a
write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D[x:0].
NWS0,
NWS1,
Input-
Synchronous
Nibble Write Select 0, 1
− Active LOW (CY7C1511JV18 Only). Sampled on the rising edge of the K
and K clocks when write operations are active. Used to select which nibble is written into the device during
the current portion of the write operations. NWS0 controls D[3:0] and NWS1 controls D[7:4].
All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select
ignores the corresponding nibble of data and it is not written into the device.
BWS0,
BWS1,
BWS2,
BWS3
Input-
Synchronous
Byte Write Select 0, 1, 2, and 3
− Active LOW. Sampled on the rising edge of the K and K clocks when
write operations are active. Used to select which byte is written into the device during the current portion
of the write operations. Bytes not written remain unaltered.
CY7C1526JV18
− BWS
0 controls D[8:0]
CY7C1513JV18
− BWS
0 controls D[8:0] and BWS1 controls D[17:9].
CY7C1515JV18
− BWS
0 controls D[8:0], BWS1 controls D[17:9],
BWS2 controls D[26:18] and BWS3 controls D[35:27].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and it is not written into the device.
A
Input-
Synchronous
Address Inputs. Sampled on the rising edge of the K clock during active read and write operations. These
address inputs are multiplexed for both read and write operations. Internally, the device is organized as
8M x 8 (4 arrays each of 2M x 8) for CY7C1511JV18, 8M x 9 (4 arrays each of 2M x 9) for CY7C1526JV18,
4M x 18 (4 arrays each of 1M x 18) for CY7C1513JV18 and 2M x 36 (4 arrays each of 512K x 36) for
CY7C1515JV18. Therefore, only 21 address inputs are needed to access the entire memory array of
CY7C1511JV18 and CY7C1526JV18, 20 address inputs for CY7C1513JV18 and 19 address inputs for
CY7C1515JV18. These inputs are ignored when the appropriate port is deselected.
Q[x:0]
Outputs-
Synchronous
Data Output Signals. These pins drive out the requested data when the read operation is active. Valid
data is driven out on the rising edge of the C and C clocks during read operations, or K and K when in
single clock mode. On deselecting the read port, Q[x:0] are automatically tri-stated.
CY7C1511JV18
− Q
[7:0]
CY7C1526JV18
− Q
[8:0]
CY7C1513JV18
− Q
[17:0]
CY7C1515JV18
− Q
[35:0]
RPS
Input-
Synchronous
Read Port Select
− Active LOW. Sampled on the rising edge of positive input clock (K). When active, a
read operation is initiated. Deasserting deselects the read port. When deselected, the pending access is
allowed to complete and the output drivers are automatically tri-stated following the next rising edge of
the C clock. Each read access consists of a burst of four sequential transfers.
C
Input Clock
Positive Input Clock for Output Data. C is used in conjunction with C to clock out the read data from
the device. C and C can be used together to deskew the flight times of various devices on the board back
to the controller. See Application Example on page 10 for further details.
C
Input Clock
Negative Input Clock for Output Data. C is used in conjunction with C to clock out the read data from
the device. C and C can be used together to deskew the flight times of various devices on the board back
to the controller. See Application Example on page 10 for further details.
K
Input Clock
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising
edge of K.
K
Input Clock
Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and
to drive out data through Q[x:0] when in single clock mode.
[+] Feedback


Similar Part No. - CY7C1511JV18-300BZXC

ManufacturerPart #DatasheetDescription
logo
Cypress Semiconductor
CY7C1511AV18 CYPRESS-CY7C1511AV18 Datasheet
709Kb / 31P
   72-Mbit QDR??II SRAM 4-Word Burst Architecture
CY7C1511AV18-167BZC CYPRESS-CY7C1511AV18-167BZC Datasheet
709Kb / 31P
   72-Mbit QDR??II SRAM 4-Word Burst Architecture
CY7C1511AV18-167BZI CYPRESS-CY7C1511AV18-167BZI Datasheet
709Kb / 31P
   72-Mbit QDR??II SRAM 4-Word Burst Architecture
CY7C1511AV18-167BZXC CYPRESS-CY7C1511AV18-167BZXC Datasheet
709Kb / 31P
   72-Mbit QDR??II SRAM 4-Word Burst Architecture
CY7C1511AV18-167BZXI CYPRESS-CY7C1511AV18-167BZXI Datasheet
709Kb / 31P
   72-Mbit QDR??II SRAM 4-Word Burst Architecture
More results

Similar Description - CY7C1511JV18-300BZXC

ManufacturerPart #DatasheetDescription
logo
Cypress Semiconductor
CY7C1511KV18 CYPRESS-CY7C1511KV18_09 Datasheet
837Kb / 31P
   72-Mbit QDR II SRAM 4-Word Burst Architecture
CY7C1561KV18 CYPRESS-CY7C1561KV18 Datasheet
833Kb / 28P
   72-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1511V18 CYPRESS-CY7C1511V18 Datasheet
381Kb / 23P
   72-Mbit QDR??II SRAM 4-Word Burst Architecture
CY7C2561KV18 CYPRESS-CY7C2561KV18 Datasheet
845Kb / 29P
   72-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1511KV18 CYPRESS-CY7C1511KV18_11 Datasheet
807Kb / 33P
   72-Mbit QDR II SRAM 4-Word Burst Architecture
CY7C1511AV18 CYPRESS-CY7C1511AV18 Datasheet
709Kb / 31P
   72-Mbit QDR??II SRAM 4-Word Burst Architecture
CY7C1513KV18 CYPRESS-CY7C1513KV18 Datasheet
831Kb / 31P
   72-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1511V18 CYPRESS-CY7C1511V18_06 Datasheet
464Kb / 28P
   72-Mbit QDR?? II SRAM 4-Word Burst Architecture
CY7C1510KV18 CYPRESS-CY7C1510KV18_09 Datasheet
836Kb / 30P
   72-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1510JV18 CYPRESS-CY7C1510JV18_09 Datasheet
654Kb / 26P
   72-Mbit QDR??II SRAM 2-Word Burst Architecture
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com