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CY7C1511JV18, CY7C1526JV18
CY7C1513JV18, CY7C1515JV18
Document Number: 001-12560 Rev. *E
Page 3 of 29
Logic Block Diagram (CY7C1513JV18)
Logic Block Diagram (CY7C1515JV18)
CLK
A(19:0)
Gen.
K
K
Control
Logic
Address
Register
D[17:0]
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
36
20
72
18
BWS[1:0]
VREF
Write
Reg
36
A(19:0)
20
18
CQ
CQ
DOFF
Q[17:0]
18
18
18
18
Write
Reg
Write
Reg
Write
Reg
C
C
CLK
A(18:0)
Gen.
K
K
Control
Logic
Address
Register
D[35:0]
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
72
19
144
36
BWS[3:0]
VREF
Write
Reg
72
A(18:0)
19
36
CQ
CQ
DOFF
Q[35:0]
36
36
36
36
Write
Reg
Write
Reg
Write
Reg
C
C
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