CY7C1392JV18, CY7C1992JV18
CY7C1393JV18, CY7C1394JV18
Document #: 001-44698 Rev. *A
Page 9 of 26
Echo Clocks
Echo clocks are provided on the DDR-II to simplify data capture
on high-speed systems. Two echo clocks are generated by the
DDR-II. CQ is referenced with respect to C and CQ is referenced
with respect to C. These are free running clocks and are synchro-
nized to the output clock of the DDR-II. In the single clock mode,
CQ is generated with respect to K and CQ is generated with
respect to K. The timing for the echo clocks is shown in Switching
Characteristics on page 22.
DLL
These chips use a Delay Lock Loop (DLL) that is designed to
function between 120 MHz and the specified maximum clock
frequency. During power up, when the DOFF is tied HIGH, the
DLL is locked after 1024 cycles of stable clock. The DLL is also
reset by slowing or stopping the input clocks K and K for a
minimum of 30 ns. However, it is not necessary to reset the DLL
to lock it to the desired frequency. The DLL automatically locks
1024 clock cycles after a stable clock is presented. Disable the
DLL by applying ground to the DOFF pin. When the DLL is turned
off, the device behaves in DDR-I mode (with one cycle latency
and a longer access time). For information refer to the application
note
AN5062
‘DLL
Considerations
in
QDRII/DDRII/QDRII+/DDRII+’.
Application Example
Figure 1 shows four DDR-II SIO used in an application.
Figure 1. Application Example
LD
#
R/W
#
B
W
#
Vt = VREF
CC#
CQ
CQ#
K#
ZQ
Q
D
K
CC# K
BUS
MASTER
(CPU
or
ASIC)
SRAM 1
SRAM 4
DATA IN
DATA OUT
Address
LD#
R/W#
BWS#
SRAM 1 Input CQ
SRAM 1 Input CQ#
SRAM 4 Input CQ
SRAM 4 Input CQ#
Source K
Source K#
Delayed K
Delayed K#
R=50Ohms
R = 250Ohms
CQ
CQ#
K#
ZQ
Q
LD
#
R/W
#
B
W
S
#
LD
#
R/W
#
Vt
Vt
Vt
R
R
R
A
A
D
R = 250Ohms
B
W
S
#
[+] Feedback
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
