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ISL6334AR5368 Datasheet(PDF) 20 Page - Intersil Corporation |
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ISL6334AR5368 Datasheet(HTML) 20 Page - Intersil Corporation |
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20 / 30 page  20 FN6839.2 September 7, 2010 Assuming the microprocessor controls the VID change at 1-bit every tVID, the relationship between the time constant of RREF and CREF network and tVID is given by Equation 13. During dynamic VID transition and VID steps up, the overcurrent trip point increases by 140% to avoid falsely triggering OCP circuits, while the overvoltage trip point is set to its maximum VID OVP trip level. If the dynamic VID occurs at PSI# asserted, the system should exit PSI# and complete the transition, and then resume PSI# operation 50µs after the transition. Operation Initialization Prior to converter initialization, proper conditions must exist on the enable inputs and VCC. When the conditions are met, the controller begins soft-start. Once the output voltage is within the proper window of operation, VR_RDY asserts logic high. Enable and Disable While in shutdown mode, the PWM outputs are held in a high- impedance state to assure the drivers remain off. The following input conditions must be met before the ISL6334AR5368 is released from shutdown mode. 1. The bias voltage applied at VCC must reach the internal power-on reset (POR) rising threshold. Once this threshold is reached, proper operation of all aspects of the ISL6334AR5368 are guaranteed. Hysteresis between the rising and falling thresholds assure that once enabled, ISL6334AR5368 will not inadvertently turn off unless the bias voltage drops substantially (see “Electrical Specifications” table beginning on page 8). 2. The ISL6334AR5368 features an enable input (EN_PWR) for power sequencing between the controller bias voltage and another voltage rail. The enable comparator holds the ISL6334AR5368 in shutdown until the voltage at EN_PWR rises above 0.875V. The enable comparator has about 130mV of hysteresis to prevent bounce. It is important that the driver reach their POR level before the ISL6334AR5368 becomes enabled. The schematic in Figure 8 demonstrates sequencing the ISL6334AR5368 with the ISL66xx family of Intersil MOSFET drivers, which require 12V bias. 3. The voltage on EN_VTT must be higher than 0.875V to enable the controller. This pin is typically connected to the output of VTT VR. When all conditions previously mentioned are satisfied, ISL6334AR5368 begins the soft-start and ramps the output voltage to 1.1V first. After remaining at 1.1V for some time, ISL6334AR5368 reads the VID code at VID input pins. If the VID code is valid, ISL6334AR5368 will regulate the output to the final VID setting. If the VID code is OFF code, ISL6334AR5368 will shut down, and cycling VCC, EN_PWR or EN_VTT is needed to restart. Soft-Start ISL6334AR5368 based VR has 4 periods during soft-start, as shown in Figure 9. After VCC, EN_VTT and EN_PWR reach their POR/enable thresholds, the controller will have a fixed delay period tD1. After this delay period, the VR will begin first soft-start ramp until the output voltage reaches 1.1V Vboot voltage. Then, the controller will regulate the VR voltage at 1.1V for another fixed period tD3. At the end of tD3 period, ISL6334AR5368 reads the VID signals. If the VID code is valid, ISL6334AR5368 will initiate the second soft-start ramp until the voltage reaches the VID voltage minus offset voltage. The soft-start time is the sum of the 4 periods as shown in Equation 14. tD1 is a fixed delay with the typical value as 1.36ms. tD3 is determined by the fixed 85µs plus the time to obtain valid VID voltage. If the VID is valid before the output reaches the 1.1V, the minimum time to validate the VID input is 500ns. Therefore, the minimum tD3 is about 86µs. During tD2 and tD4, ISL6334AR5368 digitally controls the DAC voltage change at 6.25mV per step. The time for each step is determined by the frequency of the soft-start oscillator, which is defined by the resistor RSS from SS pin to GND. The second soft-start ramp time tD2 and tD4 can be calculated based on Equations 15 and 16: C REF RREF t VID = (EQ. 13) FIGURE 8. POWER SEQUENCING USING THRESHOLD- SENSITIVE ENABLE (EN) FUNCTION - + 0.875V EXTERNAL CIRCUIT ISL6334AR5368 EN_PWR +12V POR CIRCUIT 100k Ω 9.1k Ω ENABLE COMPARATOR SOFT-START AND FAULT LOGIC EN_VTT VCC + - 0.875V INTERNAL CIRCUIT t SS t D1 t D2 t D3 t D4 ++ + = (EQ. 14) t D2 1.1xR SS 6.25x25 ------------------------ μs () = (EQ. 15) ISL6334AR5368 |
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