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CY7C1422JV18, CY7C1429JV18
CY7C1423JV18, CY7C1424JV18
Document #: 001-44699 Rev. *B
Page 2 of 28
Logic Block Diagram (CY7C1422JV18)
Logic Block Diagram (CY7C1429JV18)
CLK
A(20:0)
Gen.
K
K
Control
Logic
Address
Register
D[7:0]
Read Data Reg.
LD
Q[7:0]
Reg.
Reg.
Reg.
8
16
8
NWS[1:0]
VREF
Write
Data Reg
8
8
21
8
R/W
LD
R/W
CQ
CQ
DOFF
Write
Data Reg
Control
Logic
C
C
8
CLK
A(20:0)
Gen.
K
K
Control
Logic
Address
Register
D[8:0]
Read Data Reg.
LD
Q[8:0]
Reg.
Reg.
Reg.
9
18
9
BWS[0]
VREF
Write
Data Reg
9
9
21
9
R/W
LD
R/W
CQ
CQ
DOFF
Write
Data Reg
Control
Logic
C
C
9
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