CY7C1392JV18, CY7C1992JV18
CY7C1393JV18, CY7C1394JV18
Document #: 001-44698 Rev. *A
Page 8 of 26
Functional Overview
The CY7C1392JV18, CY7C1992JV18, CY7C1393JV18, and
CY7C1394JV18 are synchronous pipelined Burst SRAMs
equipped with a DDR-II Separate IO interface, which operates
with a read latency of one and half cycles when DOFF pin is tied
HIGH. When DOFF pin is set LOW or connected to VSS the
device behaves in DDR-I mode with a read latency of one clock
cycle.
Accesses are initiated on the rising edge of the positive input
clock (K). All synchronous input timing is referenced from the
rising edge of the input clocks (K and K) and all output timing is
referenced to the rising edge of the output clocks (C/C, or K/K
when in single clock mode).
All synchronous data inputs (D[x:0]) pass through input registers
controlled by the rising edge of the input clocks (K and K). All
synchronous data outputs (Q[x:0]) pass through output registers
controlled by the rising edge of the output clocks (C/C or K/K
when in single-clock mode).
All synchronous control (R/W, LD, BWS[0:X]) inputs pass through
input registers controlled by the rising edge of the input clock (K).
CY7C1393JV18 is described in the following sections. The same
basic descriptions apply to CY7C1392JV18, CY7C1992JV18,
and CY7C1394JV18.
Read Operations
The CY7C1393JV18 is organized internally as two arrays of
512K x 18. Accesses are completed in a burst of two sequential
18-bit data words. Read operations are initiated by asserting
R/W HIGH and LD LOW at the rising edge of the positive input
clock (K). The address presented to address inputs is stored in
the read address register. Following the next K clock rise, the
corresponding lowest order 18-bit word of data is driven onto the
Q[17:0] using C as the output timing reference. On the
subsequent rising edge of C, the next 18-bit data word is driven
onto the Q[17:0]. The requested data is valid 0.45 ns from the
rising edge of the output clock (C/C, or K/K when in single clock
mode). Read accesses are initiated on every rising edge of the
positive input clock (K). This pipelines the data flow such that
data is transferred out of the device on every rising edge of the
output clocks, C/C (or K/K when in single clock mode).
The CY7C1393JV18 first completes the pending read
transactions, when read access is deselected. Synchronous
internal circuitry automatically tri-states the output following the
next rising edge of the positive output clock (C).
Write Operations
Write operations are initiated by asserting R/W LOW and LD
LOW at the rising edge of the positive input clock (K). The
address presented to address inputs is stored in the write
address register. On the following K clock rise the data presented
to D[17:0] is latched and stored into the 18-bit write data register,
provided BWS[1:0] are both asserted active. On the subsequent
rising edge of the negative input clock (K) the information
presented to D[17:0] is also stored into the write data register,
provided BWS[1:0] are both asserted active. The 36 bits of data
are then written into the memory array at the specified location.
Write accesses are initiated on every rising edge of the positive
input clock (K). This pipelines the data flow such that 18 bits of
data can be transferred into the device on every rising edge of
the input clocks (K and K).
When Write access is deselected, the device ignores all inputs
after the pending write operations are completed.
Byte Write Operations
Byte write operations are supported by the CY7C1393JV18. A
write operation is initiated as described in the section Write
Operations on page 8. The bytes that are written are determined
by BWS0 and BWS1, which are sampled with each set of 18-bit
data words. Asserting the appropriate Byte Write Select input
during the data portion of a write latches the data being
presented and writes it into the device. Deasserting the Byte
Write Select input during the data portion of a write enables the
data stored in the device for that byte to remain unaltered. This
feature is used to simplify read, modify, and write operations to
a byte write operation.
Single Clock Mode
The CY7C1393JV18 is used with a single clock that controls
both the input and output registers. In this mode the device
recognizes only a single pair of input clocks (K and K) that control
both the input and output registers. This operation is identical to
the operation if the device had zero skew between the K/K and
C/C clocks. All timing parameters remain the same in this mode.
To use this mode of operation, tie C and C HIGH at power on.
This function is a strap option and not alterable during device
operation.
DDR Operation
The CY7C1393JV18 enables high performance operation
through high clock frequencies (achieved through pipelining) and
double data rate mode of operation.
If a read occurs after a write cycle, address and data for the write
are stored in registers. Store the write information because the
SRAM cannot perform the last word write to the array without
conflicting with the read. The data stays in this register until the
next write cycle occurs. On the first write cycle after the reads,
the stored data from the earlier write is written into the SRAM
array. This is called a posted write.
Depth Expansion
Depth expansion requires replicating the LD control signal for
each bank. All other control signals are common between banks
as appropriate.
Programmable Impedance
Connect an external resistor, RQ, between the ZQ pin on the
SRAM and VSS to enable the SRAM to adjust its output driver
impedance. The value of RQ is five times the value of the
intended line impedance driven by the SRAM. The allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15 percent is between 175
Ω and 350Ω, with VDDQ =1.5V.
The output impedance is adjusted every 1024 cycles at power
up to account for drifts in supply voltage and temperature.
[+] Feedback
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
