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CY7C1011CV33-10ZSXA Datasheet(PDF) 1 Page - Cypress Semiconductor

Part # CY7C1011CV33-10ZSXA
Description  2-Mbit (128K x 16) Static RAM
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1011CV33-10ZSXA Datasheet(HTML) 1 Page - Cypress Semiconductor

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CY7C1011CV33
2-Mbit (128K x 16) Static RAM
Cypress Semiconductor Corporation
198 Champion Court
San Jose
, CA 95134-1709
408-943-2600
Document Number: 38-05232 Rev. *H
Revised February 23, 2009
Features
Temperature ranges
Industrial: –40°C to 85°C
Automotive-A: –40°C to 85°C
Automotive-E: –40°C to 125°C
Pin and function compatible with CY7C1011BV33
High speed
tAA = 10 ns (Industrial and Automotive-A)
tAA = 12 ns (Automotive-E)
Low active power
360 mW (max) (Industrial and Automotive-A)
Data Retention at 2.0
Automatic power down when deselected
Independent control of upper and lower bits
Easy memory expansion with CE and OE features
Available in Pb-free 44-pin TSOP II, 44-pin TQFP and non
Pb-free 48-Ball VFBGA packages
Functional Description
The CY7C1011CV33 is a high performance CMOS static RAM
organized as 131,072 words by 16 bits. This device has an
automatic power down feature that significantly reduces power
consumption when deselected.
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O0 through I/O7), is written into the location
specified on the address pins (A0 through A16). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A16).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appear on I/O0 to I/O7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O8 to I/O15. For more information, see the “Truth
Table” on page 9 for a complete description of Read and Write
modes.
The input and output pins (I/O0 through I/O15) are placed in a
high impedance state when the device is deselected (CE HIGH),
the outputs are disabled (OE HIGH), the BHE and BLE are
disabled (BHE, BLE HIGH), or during a write operation (CE LOW
and WE LOW).
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
Logic Block Diagram
128K x 16
RAM Array
I/O0–I/O7
A0
A1
A2
A3
A6
COLUMN DECODER
INPUT BUFFER
OE
A4
A5
I/O8–I/O15
WE
BLE
BHE
A8
A7
CE
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