CY7C107D
CY7C1007D
1-Mbit (1M x 1) Static RAM
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
, CA 95134-1709
•
408-943-2600
Document #: 38-05469 Rev. *E
Revised February 22, 2007
Features
• Pin- and function-compatible with CY7C107B/CY7C1007B
• High speed
—tAA = 10 ns
• Low Active Power
—ICC = 80 mA @ 10 ns
• Low CMOS Standby Power
—ISB2 = 3 mA
• 2.0V Data Retention
• Automatic power-down when deselected
• CMOS for optimum speed/power
• TTL-compatible inputs and outputs
• CY7C107D available in Pb-free 28-pin 400-Mil wide Molded
SOJ package. CY7C1007D available in Pb-free 28-pin
300-Mil wide Molded SOJ package
Functional Description [1]
The CY7C107D and CY7C1007D are high-performance
CMOS static RAMs organized as 1,048,576 words by 1 bit.
Easy memory expansion is provided by an active LOW Chip
Enable (CE) and tri-state drivers. These devices have an
automatic
power-down
feature
that
reduces
power
consumption by more than 65% when deselected. The output
pin (DOUT) is placed in a high-impedance state when:
• Deselected (CE HIGH)
• When the write operation is active (CE and WE LOW)
Write to the device by taking Chip Enable (CE) and Write
Enable (WE) inputs LOW. Data on the input pin (DIN) is written
into the memory location specified on the address pins (A0
through A19).
Read from the device by taking Chip Enable (CE) LOW while
while forcing Write Enable (WE) HIGH. Under these condi-
tions, the contents of the memory location specified by the
address pins appears on the data output (DOUT) pin.
Logic Block Diagram
POWER
DOWN
CE
WE
A0
A1
A2
A3
A4
A5
A6
A7
A8
1M x 1
ARRAY
INPUT BUFFER
COLUMN DECODER
DIN
DOUT
Note
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
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