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CY7C144-15AXI Datasheet(PDF) 3 Page - Cypress Semiconductor

Part # CY7C144-15AXI
Description  8K x 8/9 Dual-Port Static RAM with SEM, INT, BUSY
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C144-15AXI Datasheet(HTML) 3 Page - Cypress Semiconductor

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CY7C144, CY7C145
Document #: 38-06034 Rev. *E
Page 3 of 20
Table 1. Selection Guide
Description
7C144-15
7C145-15
7C144-25
7C145-25
7C144-35
7C145-35
7C144-55
7C145-55
Unit
Maximum Access Time
15
25
35
55
ns
Maximum Operating Current
220
180
160
160
mA
Maximum Standby Current for ISB1
60
40
30
30
mA
Table 2. Pin Definitions
Left Port
Right Port
Description
I/O0L−7L(8L) I/O0R−7R(8R) Data bus Input/Output
A0L−12L
A0R−12R
Address Lines
CEL
CER
Chip Enable
OEL
OER
Output Enable
R/WL
R/WR
Read/Write Enable
SEML
SEMR
Semaphore Enable. When asserted LOW, allows access to eight semaphores. The three least significant
bits of the address lines will determine which semaphore to write or read. The I/O0 pin is used when writing
to a semaphore. Semaphores are requested by writing a 0 into the respective location.
INTL
INTR
Interrupt Flag. INTL is set when right port writes location 1FFE and is cleared when left port reads location
1FFE. INTR is set when left port writes location 1FFF and is cleared when right port reads location 1FFF.
BUSYL
BUSYR
Busy Flag
M/S
Master or Slave Select
VCC
Power
GND
Ground
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