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CY7C0430BV
CY7C0430CV
Document #: 38-06027 Rev. *B
Page 11 of 37
tCKLZ[9]
Clock HIGH to Output Low-Z
1
1
ns
tSINT
Clock to INT Set Time
1
7.5
1
10
ns
tRINT
Clock to INT Reset Time
1
7.5
1
10
ns
tSCINT
Clock to CNTINT Set Time
1
7.5
1
10
ns
tRCINT
Clock to CNTINT Reset Time
1
7.5
1
10
ns
Master Reset Timing
tRS
Master Reset Pulse Width
7.5
10
ns
tRSR
Master Reset Recovery Time
7.5
10
ns
tROF
Master Reset to Output Flags Reset Time
6.5
8
ns
Port to Port Delays
tCCS[6]
Clock to Clock Set-up Time (time required after a write
before you can read the same address location)
6.5
9
ns
JTAG Timing and Switching Waveforms
Parameter
Description
Quadport DSE Family
Unit
–133/–100
Min.
Max.
fJTAG
Maximum JTAG TAP Controller Frequency
10
MHz
tTCYC
TCK Clock Cycle Time
100
ns
tTH
TCK Clock High Time
40
ns
tTL
TCK Clock Low Time
40
ns
tTMSS
TMS Set-up to TCK Clock Rise
20
ns
tTMSH
TMS Hold After TCK Clock Rise
20
ns
tTDIS
TDI Set-up to TCK Clock Rise
20
ns
tTDIH
TDI Hold after TCK Clock Rise
20
ns
tTDOV
TCK Clock Low to TDO Valid
20
ns
tTDOX
TCK Clock Low to TDO Invalid
0
ns
fBIST
Maximum CLKBIST Frequency
50
MHz
tBH
CLKBIST High Time
6
ns
tBL
CLKBIST Low Time
6
ns
Switching Characteristics Over the Industrial Operating Range (continued)[6]
Parameter
Description
CY7C0430BV and CY7C0430CV
Unit
–133
–100
Min.
Max.
Min.
Max.
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