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CY7C0430BV
CY7C0430CV
Document #: 38-06027 Rev. *B
Page 10 of 37
Switching Characteristics Over the Industrial Operating Range [6]
Parameter
Description
CY7C0430BV and CY7C0430CV
Unit
–133
–100
Min.
Max.
Min.
Max.
fMAX2[7]
Maximum Frequency
133
100
MHz
tCYC2[7]
Clock Cycle Time
7.5
10
ns
tCH2
Clock HIGH Time
3
4
ns
tCL2
Clock LOW Time
3
4
ns
tR
Clock Rise Time
2
3
ns
tF
Clock Fall Time
2
3
ns
tSA
Address Set-up Time
2.3
3
ns
tHA
Address Hold Time
0.7
0.7
ns
tSC
Chip Enable Set-up Time
2.3
3
ns
tHC
Chip Enable Hold Time
0.7
0.7
ns
tSW
R/W Set-up Time
2.3
3
ns
tHW
R/W Hold Time
0.7
0.7
ns
tSD
Input Data Set-up Time
2.3
3
ns
tHD
Input Data Hold Time
0.7
0.7
ns
tSB
Byte Set-up Time
2.3
3
ns
tHB
Byte Hold Time
0.7
0.7
ns
tSCLD
CNTLD Set-up Time
2.3
3
ns
tHCLD
CNTLD Hold Time
0.7
0.7
ns
tSCINC
CNTINC Set-up Time
2.3
3
ns
tHCINC
CNTINC Hold Time
0.7
0.7
ns
tSCRST
CNTRST Set-up Time
2.3
3
ns
tHCRST
CNTRST Hold Time
0.7
0.7
ns
tSCRD
CNTRD Set-up Time
2.3
3
ns
tHCRD
CNTRD Hold Time
0.7
0.7
ns
tSMLD
MKLD Set-up Time
2.3
3
ns
tHMLD
MKLD Hold Time
0.7
0.7
ns
tSMRD
MKRD Set-up Time
2.3
3
ns
tHMRD
MKRD Hold Time
0.7
0.7
ns
tOE
Output Enable to Data Valid
6.5
8
ns
tOLZ[8]
OE to Low-Z
1
1
ns
tOHZ[8]
OE to High-Z
1
6
1
7
ns
tCD2
Clock to Data Valid
4.2
5
ns
tCA2
Clock to Counter Address Readback Valid
4.7
5
ns
tCM2
Clock to Mask Register Readback Valid
4.7
5
ns
tDC
Data Output Hold After Clock HIGH
1
1
ns
tCKHZ[9]
Clock HIGH to Output High-Z
1
4.8
1
6.8
ns
Notes:
6. If data is simultaneously written and read to the same address location and tCCS is violated, the data read from the address, as well as the subsequent data
remaining in the address is undefined.
7. fMAX2 for commercial is 135 MHz. tCYC2 Min. for commercial is 7.4 ns.
8. This parameter is guaranteed by design, but it is not production tested.
9. Valid for both address and data outputs.
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