9 / 15 page
CY7C132, CY7C136
CY7C136A, CY7C142, CY7C146
Document #: 38-06031 Rev. *E
Page 9 of 15
Figure 8. Write Cycle No. 2 (R/W Three-States Data I/Os—Either Port)[12, 21]
Figure 9. Busy Timing Diagram No. 1 (CE Arbitration)
Switching Waveforms (continued)
tAW
tWC
tSCE
tSA
tPWE
tHD
tSD
tHZWE
tHA
HIGH IMPEDANCE
CE
R/W
ADDRESS
DOUT
DATAIN
tLZWE
DATA VALID
ADDRESS MATCH
tPS
CEL Valid First:
tBLC
tBHC
ADDRESS MATCH
tPS
tBLC
tBHC
BUSYL
CER
CEL
ADDRESSL,R
BUSYR
CEL
CER
ADDRESSL,R
CER Valid First:
Note
21. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in a high impedance state.
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