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ISL62870HRUZ Datasheet(PDF) 6 Page - Intersil Corporation |
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ISL62870HRUZ Datasheet(HTML) 6 Page - Intersil Corporation |
6 / 16 page 6 FN6708.0 August 14, 2008 Functional Pin Descriptions GND (Pin 1) IC ground for bias supply and signal reference. EN (Pin 2) Enable input for the IC. Pulling EN above the VENTHR rising threshold voltage initializes the soft-start sequence. NC (Pins 3, 5) No internal connection. Pins 3 and 5 should be connected to the GND pin. SREF (Pin 4) Soft-start programming capacitor input. Connects internally to the inverting input of the VSET voltage setpoint amplifier. PGOOD (Pin 6) Power-good open-drain indicator output. This pin changes to high impedance when the converter is able to supply regulated voltage. The pull-down resistance between the PGOOD pin and the GND pin identifies which protective fault has shut down the regulator. See Table 1 on page 10. FB (Pin 7) Voltage feedback sense input. Connects internally to the inverting input of the control-loop error amplifier. The converter is in regulation when the voltage at the FB pin equals the voltage on the SREF pin. The control loop compensation network connects between the FB pin and the converter output. See Figure 8 on page 10. VO (Pin 8) Output voltage sense input for the R3 modulator. The VO pin also serves as the reference input for the overcurrent detection circuit. See Figure 5 on page 7. OCSET (Pin 9) Input for the overcurrent detection circuit. The overcurrent setpoint programming resistor ROCSET connects from this pin to the sense node. See “OVERCURRENT PROGRAMMING CIRCUIT” on page 7. PHASE (Pin 10) Return current path for the UGATE high-side MOSFET driver. VIN sense input for the R3 modulator. Inductor current polarity detector input. Connect to junction of output inductor, high-side MOSFET, and low-side MOSFET. See “Application Schematics” on page 3 (Figures 2 and 3). UGATE (Pin 11) High-side MOSFET gate driver output. Connect to the gate terminal of the high-side MOSFET of the converter. BOOT (Pin 12) Positive input supply for the UGATE high-side MOSFET gate driver. The BOOT pin is internally connected to the cathode of the Schottky boot-strap diode. Connect an MLCC between the BOOT pin and the PHASE pin. VCC (Pin 13) Input for the IC bias voltage. Connect +5V to the VCC pin and decouple with at least a 1µF MLCC to the GND pin. See “Application Schematics” on page 3 (Figures 2 and 3). PVCC (Pin 14) Input for the LGATE and UGATE MOSFET driver circuits. The PVCC pin is internally connected to the anode of the Schottky boot-strap diode. Connect +5V to the PVCC pin and decouple with a 10µF MLCC to the PGND pin. See “Application Schematics” on page 3 (Figures 2 and 3). LGATE (Pin 15) Low-side MOSFET gate driver output. Connect to the gate terminal of the low-side MOSFET of the converter. PGND (Pin 16) Return current path for the LGATE MOSFET driver. Connect to the source of the low-side MOSFET. Setpoint Reference Voltage The 500mV output of the setpoint reference voltage (VSREF) appears at the SREF pin. This signal is the output of the current limited voltage follower that buffers an internal 500mV voltage reference (VREF.) The converter is in regulation when the voltage at the FB pin (VFB) equals the VSREF voltage at the SREF pin. Both of these pins are measured relative to the GND pin, not the PGND pin. The feedback voltage-divider network consisting of offset resistor (ROFS) and loop-compensation resistor (RFB) scale down the converter output voltage (VOUT) such that the voltage VFB equals VSREF when VOUT equals the desired output voltage of the converter. The voltage-divider relation is given in Equation 1: Where: -VFB = VSREF -RFB is the loop-compensation feedback resistor that connects from the FB pin to the converter output -ROFS is the voltage-scaling programming resistor that connects from the FB pin to the GND pin The value of offset resistor ROFS must be recalculated whenever the value of loop-compensation resistor RFB has been changed. Calculation of ROFS is written as shown in Equation 2: V FB V OUT R OFS R FB R OFS + ---------------------------------- ⋅ = (EQ. 1) R OFS V SREF R ⋅ FB V OUT V SREF – ----------------------------------------- = (EQ. 2) ISL62870 |
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