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TSV633AIST Datasheet(PDF) 7 Page - STMicroelectronics |
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TSV633AIST Datasheet(HTML) 7 Page - STMicroelectronics |
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7 / 26 page  TSV63x Electrical characteristics Doc ID 15688 Rev 2 7/26 Table 5. VCC+ = +3.3 V, VCC- = 0 V, Vicm = VCC/2, Tamb = 25° C, RL connected to VCC/2 (unless otherwise specified) Symbol Parameter Conditions Min. Typ. Max. Unit DC performance Vio Offset voltage TSV63x TSV63xA TSV633AIST - MiniSO10 3 0.8 1 mV Tmin < Top < Tmax - TSV63x Tmin < Top < Tmax - TSV63xA Tmin < Top < Tmax - TSV633AIST 4.5 2 2.2 mV DVio Input offset voltage drift 2 μV/°C Iio Input offset current 110(1) pA Tmin < Top < Tmax 1 100 pA Iib Input bias current 110(1) pA Tmin < Top < Tmax 1 100 pA CMR Common mode rejection ratio 20 log ( ΔVic/ΔVio) 0V to 3.3V, Vout = 1.65 V 57 79 dB Tmin < Top < Tmax 53 Avd Large signal voltage gain RL =10kΩ, Vout = 0.5 V to 2.8 V 88 98 dB Tmin < Top < Tmax 83 VOH High level output voltage RL =10kΩ Tmi. < Top < Tmax 35 50 5 mV VOL Low level output voltage RL =10kΩ Tmin < Top < Tmax 435 50 mV Iout Isink Vo = 3.3 V 23 45 mA Tmin < Top < Tmax 20 Isource Vo = 0 V 23 38 mA Tmin < Top < Tmax 20 ICC Supply current (per operator) No load, Vout = 1.75 V 43 55 64 µA Tmin < Top < Tmax 66 µA AC performance GBP Gain bandwidth product RL =2kΩ, CL = 100 pF, f = 100 kHz 710 860 kHz φm Phase margin RL = 2 kΩ, CL = 100 pF 46 Degrees Gm Gain margin RL = 2 kΩ, CL = 100 pF 13 dB SR Slew rate RL =2kΩ, CL = 100 pF, AV = 1 0.22 0.29 V/ μs 1. Guaranteed by design. |
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