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UC1851 Datasheet(PDF) 4 Page - Texas Instruments |
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UC1851 Datasheet(HTML) 4 Page - Texas Instruments |
4 / 7 page UC1851 UC2851 UC3851 PWM CONTROL 1. Oscillator Generates a fixed-frequency internal clock from an external RT and CT. Frequency = KC RTCT where KC is a first-order correction factor ≈ 0.3 log (CT x 1012). 2. Ramp Generator: Develops linear ramp with slope defined externally by dV dT = sense voltage RRCR . CR is normally selected ≤ CT and its value will have some effect upon valley duty cycle. Limiting the minimum value for ISENSE into pin 11 will establish a maximum duty cycle clamp. CR terminal can be used as an input port for current mode control. 3. Error Amplifier Conventional operational amplifier for closed-loop gain and phase compensation. Low output impedance; unity-gain stable. The output is held low by the slow start voltage at turn on in order to minimize overshoot. 4. Reference Generator: Precision 5.0V for internal and external usage to 50mA. Tracking 3.0V reference for internal usage only with nominal accuracy of ±2%. 40V clamp zener for chip OV protection, 100mA maximum current. 5. PWM Comparator: Generates output pulse which starts at termination of clock pulse and ends when the ramp input crosses the lowest of two positive inputs. 6. PWM Latch: Terminates the PWM output pulse when set by inputs from either the PWM comparator, the pulse-by-pulse comparator, or the error latch. Resets with each internal clock pulse. 7. PWM Output Switch: Totem pole output stage capable of sourcing and sinking 1 amp peak current. The active "on" state is high. SEQUENCING FUNCTIONS 1. Start/UV Sense: With an increasing voltage, this comparator generates a turn-on signal and releases the slow start clamp at a start threshold. With a decreasing voltage, it generates a turn-off command at a lower level separated by a 200 µA hysteresis current. 2. Drive Switch: Disables most of the chip to hold internal current consumption low, and Driver Bias OFF, until input voltage reaches start threshold. 3. Driver Bias: Supplies drive to external circuitry upon start-up. 4. Slow Start: Clamps low to hold PWM OFF. Upon release, rises with rate controlled by RSCS for slow increase of output pulse width. Can also be used as an alternate maximum duty cycle clamp with an external voltage divider. PROTECTION FUNCTIONS 1. Error Latch: When set by momentary input, this latch insures immediate PWM shutdown and hold off until reset. Inputs to Error Latch are: a. OV > 3.2V (Typically 3V) b. Stop > 2.4V (Typically 1.6V) c. Current Sense 400mV over threshold. (Typical). Error Latch resets when slow start voltage falls to 0.4V if Reset Pin < 2.8V. With Pin 5 > 3.2V, Error Latch will remain set. 2. Current Limiting: Differential input comparator terminates individual output pulses each time sense voltage rises above threshold. When sense voltage rises to 400mV (typical) above threshold, a shutdown signal is sent to Error Latch. 3. External Stop: A voltage over 2.4 will set the Error Latch and hold the output off. A voltage less than 0.8V will defeat the error latch and prevent shutdown. A capacitor here will slow the action of the error latch for transient protection by providing a Typical Delay of 13ms/ µF. FUNCTIONAL DESCRIPTION 4 |
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