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XC6118C08AMR-G Datasheet(PDF) 18 Page - Torex Semiconductor |
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XC6118C08AMR-G Datasheet(HTML) 18 Page - Torex Semiconductor |
18 / 20 page 18/20 XC6118 Series CMOS Output (XC6118C Series) N-ch Open Drain Output (XC6118N Series) MARK VOLTAGE (V) L 0.X M 1.X N 2.X P 3.X R 4.X S 5.X MARK VOLTAGE (V) T 0.X U 1.X V 2.X X 3.X Y 4.X Z 5.X MARK VOLTAGE (V) PRODUCT SERIES 3 X.3 XC6118**3*** 0 X.0 XC6118**0*** MARK OPTIONS PRODUCT SERIES A Built-in delay capacitance pin with hysteresis 5% (TYP.) (Standard) XC6118***A** B Built-in delay capacitance pin with hysteresis less than 1% (Standard) XC6118***B** C No built-in delay capacitance pin with hysteresis 5% (TYP.) (Semi-custom) XC6118***C** D No built-in delay capacitance pin with hysteresis less than 1% (Semi-custom) XC6118***D** ■MARKING RULE ●SOT-25 ① represents output configuration and integer number of detect voltage SOT-25 (TOP VIEW) ② represents decimal number of detect voltage (ex.) ③ represents options ④⑤ represents production lot number 0 to 9 A to Z, or inverted characters of 0 to 9, A to Z repeated. (G, I, J, O, Q, and W excluded) *No character inversion used. 12 3 54 ① ② ③ ④ ⑤ |
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