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TDF8599A Datasheet(PDF) 45 Page - NXP Semiconductors |
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TDF8599A Datasheet(HTML) 45 Page - NXP Semiconductors |
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45 / 54 page  TDF8599A_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 30 June 2009 45 of 54 NXP Semiconductors TDF8599A I2C-bus controlled dual channel class-D power amplifier I2C-bus mode: dual BTL in Master mode, one BTL in Slave mode; DC offset protection enabled. (1) See Figure 3 on page 6 for a diagram of the connection for pins EN and SEL_MUTE. (2) See Section 8.3.2 on page 8 for detailed information. (3) See Section 8.5.5 on page 16 for detailed information on disabling DC offset protection. (4) See Section 8.3.4 on page 10 for detailed information on PLL operation. Fig 50. Example application diagram: dual BTL master, single BTL slave in I2C-bus mode 22 Ω 39 k Ω 20 k Ω 10 k Ω 10 k Ω ≤ 13 kΩ 10 Ω 10 Ω 22 Ω 100 µF 35 V 100 µF 35 V 100 nF 15 nF 470 nF 100 nF 15 nF 470 pF 470 pF 470 pF 470 pF CLC CIN1P 470 nF CIN1N 470 nF CIN2P 470 nF 470 nF 2.2 µF 47 µF 1 µF CIN2N LLC LLC CLC 100 nF PGND1 PGND1 VP1 VP1 VP1 VP2 VPA TDF8599A bead bead RADS bead bead OUT1N OUT1P OUT1N VP GND OUT1P VSTAB1 GNDD/HW 33 32 31 30 29 28 34 35 36 25 24 23 22 21 20 19 26 27 4 5 6 7 8 9 3 2 1 12 13 14 15 16 17 18 11 10 BOOT1N BOOT1P VP1 PGND1 PGND1 PGND2 VDDD 1000 µF 35 V 4.7 µF 100 nF 220 nF VSTAB2 DCP OSCIO 220 nF 22 Ω 10 Ω 10 Ω 22 Ω 100 nF 15 nF 100 nF 15 nF 470 pF 470 pF 470 pF 470 pF CLC LLC LLC CLC 100 nF PGND2 PGND2 VP2 VP2 OUT2P MASTER SLAVE OUT2N OUT2P OUT2N BOOT2P BOOT2N VP2 PGND2 IN2N AGND IN2P IN1P ACGND SVRR EN(1) SEL_MUTE(1) IN1N IN2N 100 nF 100 nF CACGND enable IN2P IN1P IN1N SCL SSM OSCSET VDDA SDA VPAPull-up VPull-up VPA stereo mode setting spread spectrum mode(2) DC offset protection enabled (3) DC offset protection enabled (3) MASTER MODE I2C-bus address select ADS DIAG MOD CLIP 001aak083 22 Ω 5.1 k Ω 10 k Ω 10 k Ω ≥ 33 kΩ 10 Ω 10 Ω 22 Ω 100 nF 15 nF 470 nF 100 nF 15 nF 470 pF 470 pF 470 pF 470 pF CLC CINP 470 nF CINN 470 nF 2.2 µF 47 µF LLC LLC CLC 100 nF PGND1 PGND1 VP1 VP1 TDF8599A bead RADS OUT1N OUT1P OUT3N OUT3P VSTAB1 GNDD/HW 33 32 31 30 29 28 34 35 36 25 24 23 22 21 20 19 26 27 4 5 6 7 8 9 3 2 1 12 13 14 15 16 17 18 11 10 BOOT1N BOOT1P VP1 PGND1 VDDD 4.7 µF 100 nF 220 nF VSTAB2 DCP OSCIO 220 nF 10 Ω 10 Ω 15 nF 100 nF 15 nF 470 pF 470 pF 470 pF 470 pF LLC LLC PGND2 PGND2 VP2 VP2 OUT2P OUT2N BOOT2P BOOT2N VP2 PGND2 IN2N AGND IN2P IN1P ACGND SVRR EN(1) SEL_MUTE(1) IN1N 100 nF 10 nF 270 nF CACGND IN3P IN3N SCL SSM OSCSET VDDA SDA VPull-up VPull-up VPA parallel mode setting connect to µP phase lock operation (4) SLAVE MODE I2C-bus address select ADS DIAG MOD CLIP |
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