Electronic Components Datasheet Search |
|
SE97 Datasheet(PDF) 42 Page - NXP Semiconductors |
|
SE97 Datasheet(HTML) 42 Page - NXP Semiconductors |
42 / 54 page SE97_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 6 August 2009 42 of 54 NXP Semiconductors SE97 DDR memory module temp sensor with integrated SPD, 3.3 V [1] Minimum clock frequency is 0 kHz if SMBus Time-out is disabled. [2] Delay from SDA STOP to SDA START. [3] A device must internally provide a hold time of at least 200 ns for SDA signal (referenced to the VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL. [4] Delay from SCL HIGH-to-LOW transition to SDA edges. [5] Delay from SCL LOW-to-HIGH transition to restart SDA. [6] Delay from SDA START to first SCL HIGH-to-LOW transition. [7] These parameters tested initially and after a design or process change that affects the parameter. [8] tpu(R) and tpu(W) are the delays required from the time VDD is stable until the specified operation can be initiated. Table 30. SMBus AC characteristics VDD = 1.7 V to 3.6 V; Tamb = −40 °C to +125 °C; unless otherwise specified. These specifications are guaranteed by design. The AC specifications fully meet or exceed SMBus 2.0 specifications, but allow the bus to interface with the I2C-bus from DC to 400 kHz. Symbol Parameter Conditions Standard mode Fast mode Unit Min Max Min Max fSCL SCL clock frequency 10[1] 100 10[1] 400 kHz tHIGH HIGH period of the SCL clock 70 % to 70 % 4000 - 600 - ns tLOW LOW period of the SCL clock 30 % to 30 % 4700 - 1300 - ns tto(SMBus) SMBus time-out time LOW period to reset SMBus 25 35 25 35 ms tr rise time of both SDA and SCL signals - 1000 20 300 ns tf fall time of both SDA and SCL signals - 300 - 300 ns tSU;DAT data set-up time 250 - 100 - ns th(i)(D) data input hold time [2][3] 0-0- ns tHD;DAT data hold time [4] 200 3450 200 900 ns tSU;STA set-up time for a repeated START condition [5] 4700 - 600 - ns tHD;STA hold time (repeated) START condition 30 % of SDA to 70 % of SCL [6] 4000 - 600 - ns tSU;STO set-up time for STOP condition 4000 - 600 - ns tBUF bus free time between a STOP and START condition [2] 4700 - 1300 - ns tSP pulse width of spikes that must be suppressed by the input filter -50-50 ns tVD;DAT data valid time from clock 200 - 200 - ns tf(o) output fall time - - - 250 ns tPOR power-on reset pulse time power supply falling 0.5 - 0.5 - µs EEPROM power-up timing[7] tpu(R) read power-up time [8] -1-1 ms tpu(W) write power-up time [8] -1-1 ms Write cycle limits Tcy(W) write cycle time [9] -10-10 ms |
Similar Part No. - SE97 |
|
Similar Description - SE97 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |