ADC1213D065 datasheet(10/38 Pages) NXP

Part #	ADC1213D065

Description	Dual 12-bit ADC; 65, 80, 105 or 125 Msps

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Manufacturer	NXP [NXP Semiconductors]

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10 / 38 page

ADC1213D065_080_105_125_2

Objective data sheet

Rev. 02 — 17 June 2009

10 of 38

NXP Semiconductors

ADC1213D065/080/105/125

Dual 12-bit ADC; 65, 80, 105 or 125 Msps

11. Clock and digital output timing

11.1 Serial output timings

The eye diagram of the serial output is shown in Figure 3 and Figure 4. Test conditions

are:

• 3.125 Gbps data rate

• Tamb =25˚C

• DC coupling with 2 different receiver common-mode voltages.

SFDR

spurious-free

dynamic range

fi = 3 MHz

-91

-

-91

-

-90

--90

-

dBc

fi = 30 MHz

-90

-

-90

-

-90

--89

-

dBc

fi = 70 MHz

-89

-

-89

-

-88

--87

-

dBc

fi = 170 MHz

-

86

-

86

-

85

-

85

-

dBc

IMD

intermodulation

distortion

fi = 3 MHz

-94

-

-94

-

-93

--93

-

dBc

fi = 30 MHz

-93

-

-93

-

-93

--92

-

dBc

fi = 70 MHz

-92

-

-92

-

-91

--90

-

dBc

fi = 170 MHz

-

89

-

89

-

88

-

88

-

dBc

αct(ch)

crosstalk

between

channels

fi = 70 MHz

-87

-

-85

-

-86

--85

-

dB

Table 6.

Characteristics …continued

Typical values measured at VDDA =3V, VDDD = 1.8 V, Tamb =25 °C and CL = 5 pF.

Min. and max. values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA =3V, VDDD = 1.8 V ;

Vi (INAP, INBP) − Vi (INAM, INBM) = −1 dBFS; internal reference mode; 100 Ω differential applied to serial outputs; unless

otherwise speciﬁed.

Symbol Parameter

Conditions

ADC1213D065 ADC1213D080

ADC1213D105

ADC1213D125

Unit

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Table 7.

Characteristics

Typical values measured at VDDA =3V, VDDD = 1.8 V, Tamb =25 °C and CL = 5 pF.

Min. and max. values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA =3V, VDDD = 1.8 V ;

VI (INAP, INBP) − VI (INAM, INBM) = −1 dBFS; internal reference mode; 100 Ω differential applied to serial outputs; unless

otherwise speciﬁed.

Symbol

Parameter

Conditions

ADC1213D065

ADC1213D080

ADC1213D105

ADC1213D125

Unit

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Clock timing input: pins CLKP and CLKM

fclk

clock

frequency

20

-

65

60

-

80

60

-

105

60

-

125

Msps

tlat(data)

data latency

time

17

-

20

17

-

20

17

-

20

17

-

20

clk/cy

δclk

clock duty

cycle

DCS en

30

50

70

30

50

70

30

50

70

30

50

70

%

DCS dis

45

50

55

45

50

55

45

50

55

45

50

55

%

td(s)

sampling

delay time

-

0.8

-

0.8

-

0.8

-

0.8

-

ns

twake

wake-up time

-

tbd

-

tbd

-

tbd

-

tbd

-

ns

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