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XIO2213BZAY Datasheet(PDF) 10 Page - Texas Instruments |
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XIO2213BZAY Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 199 page  XIO2213B PCI Express™ TO 1394b OHCI WITH 3-PORT PHY SCPS210D – OCTOBER 2008 – REVISED JULY 2009 www.ti.com 7-2 Command Register Description ................................................................................................ 116 7-3 Status Register Description .................................................................................................... 117 7-4 Class Code and Revision ID Registers Description ......................................................................... 118 7-5 Latency Timer and Class Cache Line Size Registers Description ........................................................ 118 7-6 Header Type and BIST Registers Description .............................................................................. 119 7-7 OHCI Base Address Register Description .................................................................................... 119 7-8 TI Base Address Register Description ........................................................................................ 120 7-9 Subsystem Vendor ID and Subsystem ID Registers Description ......................................................... 121 7-10 Interrupt Line and Interrupt Pin Registers Description ...................................................................... 122 7-11 Minimum Grant and Minimum Latency Registers Description ............................................................. 123 7-12 OHCI Control Register Description ............................................................................................ 123 7-13 Capability ID and Next Item Pointer Registers Description ................................................................ 124 7-14 Power Management Capabilities Register Description ..................................................................... 124 7-15 Power Management Control and Status Register Description ............................................................ 125 7-16 Power Management Extension Registers Description ...................................................................... 125 7-17 PCI Miscellaneous Configuration Register ................................................................................... 127 7-18 Link Enhancement Control Register Description ............................................................................ 129 7-19 Subsystem Access Register Description ..................................................................................... 130 8-1 OHCI Register Map ............................................................................................................. 131 8-2 OHCI Version Register Description ........................................................................................... 134 8-3 GUID ROM Register Description .............................................................................................. 135 8-4 Asynchronous Transmit Retries Register Description ...................................................................... 136 8-5 CSR Control Register Description ............................................................................................. 137 8-6 Configuration ROM Header Register Description ........................................................................... 138 8-7 Bus Options Register Description ............................................................................................. 139 8-8 Configuration ROM Mapping Register Description .......................................................................... 141 8-9 Posted Write Address Low Register Description ............................................................................ 141 8-10 Posted Write Address High Register Description ........................................................................... 142 8-11 Host Controller Control Register Description ................................................................................ 143 8-12 Self-ID Count Register Description ............................................................................................ 144 8-13 Isochronous Receive Channel Mask High Register Description .......................................................... 145 8-14 Isochronous Receive Channel Mask Low Register Description ........................................................... 146 8-15 Interrupt Event Register Description .......................................................................................... 147 8-16 Interrupt Mask Register Description ........................................................................................... 148 8-17 Isochronous Transmit Interrupt Event Register Description ............................................................... 150 8-18 Isochronous Receive Interrupt Event Register Description ................................................................ 151 8-19 Initial Bandwidth Available Register Description ............................................................................ 152 8-20 Initial Channels Available High Register Description ....................................................................... 153 8-21 Initial Channels Available Low Register Description ........................................................................ 153 8-22 Fairness Control Registre Description ........................................................................................ 154 8-23 Link Control Register Description ............................................................................................. 155 List of Tables 10 Submit Documentation Feedback |
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