TYPICAL APPLICATION SCHEMATIC

PTD08A020W

FAULT

PWM

SRE

INH

TEMP

VOUT

GND

IOUT

VBIAS

VIN

PTD08A010W

FAULT

PWM

SRE

INH

TEMP

VOUT

GND

IOUT

VBIAS

VIN

PTD08A010W

FAULT

PWM

SRE

INH

TEMP

VOUT

GND

IOUT

VBIAS

VIN

UCD9220

nTRST

TMS

TDI/Sync_In

TDO/Sync_Out

FLT-1A

DPWM-1A

SRE-1A

FLT-1B

DPWM-1B

SRE-1B

FLT-2A

DPWM-2A

SRE-2A

FLT-3A

DPWM-3A

SRE-3A

TMUX-0

TMUX-1

TCK

nRESET

PMBus_Clock

PMBus_Data

PMBus_Alert

PMBus_Cntl

EAP1

ADDR-0

ADDR-1

EAN1

EAP2

EAN2

Vin/Iin

Vtrack

Temperature

CS-1A

CS-1B

CS-2A

CS-3A

PowerGood

ADCref

GPIO-1

GPIO-2

+Vs2

-Vs2

+Vs1

-Vs1

Commutation

logic

PTD08A020W

UCD7230

temp

sensor

FAULT

PWM

SRE

INH

IOUT

VBIAS

VIN

TEMP

VOUT

GND

+3.3V

+3.3V

Vin

-Vs1

+Vs1

+Vs2

-Vs2

CD74HC4052

Vcc

1Y0

1Z

Gnd

1Y1

1Y2

1Y3

2Y0

2Y1

2Y2

2Y3

2Z

S1

S0

E

+3.3V

Vinput

Iin

Temperature

Vin/Iin

Temp-1

Temp-2

Temp-3

Temp-4

Temp-4

Temp-3

Temp-2

Temp-1

Vin

Vin/Iin

Temperature

* Iin Optional

Vinput

UCD9220

Figure 3 shows the UCD9220 power supply controller as part of a system that provides the regulation of two

independent power supplies. The loop for each power supply is created by the respective voltage outputs feeding

into the differential voltage error ADC (EADC) inputs, and completed by DPWM outputs feeding into the gate

drivers for each power stage (PTD modules in this example).

configured as part of the rail. (See more detail on page 19, "Flexible Rail/Power Stage Configuration".)

Figure 3. Typical Application Schematic

Copyright © 2009, Texas Instruments Incorporated

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