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TVP3409 Datasheet(PDF) 6 Page - Texas Instruments |
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TVP3409 Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 57 page  vi List of Tables Table Title Page 2–1 Feature Comparisons and Functional Differences of the TVP3409/ATT20C409, ATT21C498, and ATT20C499 2–1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2 Standard Register Set 2–2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3 State Machine Register Set 2–2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4 Indexed Register Set 2–2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5 Indexed Clock Synthesizer Configuration Registers 2–3 . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6 Standard Register Set 2–4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7 Accessing the RMR Enables Indirect Access of CR0, MIR, and DIR 2–5 . . . . . . . . . . . . 2–8 Control Register 0 2–6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9 Control Register 1 2–7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–10 Clock Synthesizer Control Register 2–8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11 Clock Synthesizer A Parameters 2–9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12 Clock Synthesizer A Register Set Fields 2–9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–13 Clock Synthesizer B Parameters 2–10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14 Clock Synthesizer B Register Set Fields 2–10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15 I/O Transition and Logic-Level Combinations that Reset the State Machine to State 0 2–12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16 Access to CR0, MIR, and DIR Registers 2–13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17 Color Modes 2–15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18 Color-Mode Speeds 2–16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19 Clock Synthesizer Reset Frequencies and FS(1,0) Terminal Logic Levels 2–18 . . . . . . . 2–20 Modulo 3 Counter Operation 2–19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21 Device Gain Factor (K) 2–20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22 RS-343A Video Output Truth Table (Blank Offset Current to Equal 7.5 IRE) 2–21 . . . . . . 2–23 RS-343A Video Output Truth Table (No Blank Offset Current) 2–22 . . . . . . . . . . . . . . . . . . 2–24 PS/2 Video Output Truth Table (No Blank Offset Current) 2–22 . . . . . . . . . . . . . . . . . . . . . |
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Similar Description - TVP3409 |
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