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TMX320C6748ZCE3 Datasheet(PDF) 9 Page - Texas Instruments |
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TMX320C6748ZCE3 Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 242 page  TMS320C6748 Fixed/Floating-Point DSP www.ti.com SPRS590 – JUNE 2009 Table 3-1. Characteristics of C6748 HARDWARE FEATURES C6748 DDR2/mDDR Controller DDR2 or Mobile DDR, 16-bit bus width, up to 150 MHz Asynchronous (8/16-bit bus width) RAM, Flash, 16-bit EMIFA SDRAM, NOR, NAND Flash Card Interface MMC and SD cards supported. 64 independent channels, 16 QDMA channels, 2 channel EDMA3 controllers, 3 transfer controllers 4 64-Bit General Purpose (configurable as 2 separate 32-bit Timers timers, 1 configurable as Watch Dog) UART 3 (each with RTS and CTS flow control) SPI 2 (Each with one hardware chip select) I2C 2 (both Master/Slave) Peripherals Multichannel Audio Serial Port [McASP] 1 (each with transmit/receive, FIFO buffer, 16 serializers) Not all peripherals pins Multichannel Buffered Serial Port [McBSP] 2 (each with transmit/receive, FIFO buffer, 16) are available at the same time (for more 10/100 Ethernet MAC with Management Data I/O 1 (MII or RMII Interface) detail, see the Device 4 Single Edge, 4 Dual Edge Symmetric, or 2 Dual Edge Configurations section). eHRPWM Asymmetric Outputs eCAP 3 32-bit capture inputs or 3 32-bit auxiliary PWM outputs UHPI 1 (16-bit multiplexed address/data) USB 2.0 (USB0) High-Speed OTG Controller with on-chip OTG PHY USB 1.1 (USB1) Full-Speed OHCI (as host) with on-chip PHY General-Purpose Input/Output Port 9 banks of 16-bit LCD Controller 1 SATA Controller 1 (Support both SATA I and SATAII) Universal Parallel Port (uPP) 1 Video Port Interface (VPIF) 1 (video in and video out) Size (Bytes) 488KB RAM, 1088KB Boot ROM DSP 32KB L1 Program (L1P)/Cache (up to 32KB) 32KB L1 Data (L1D)/Cache (up to 32KB) 256KB Unified Mapped RAM/Cache (L2) On-Chip Memory 1024KB ROM (L2) Organization DSP Memories can be made accessible to EDMA3 and other peripherals. ADDITIONAL SHARED MEMORY 128KB RAM C674x CPU ID + CPU Control Status Register (CSR.[31:16]) 0x1400 Rev ID C674x Megamodule Revision ID Register (MM_REVID[15:0]) 0x0000 Revision JTAG BSDL_ID DEVIDR0 Register 0x0B7D_102F CPU Frequency MHz 674x DSP 300 MHz Cycle Time ns 674x DSP 3.33 ns CPU Frequency MHz 674x DSP 300 MHz Cycle Time ns 674x DSP 3.33 ns Core (V) 1.2 V Voltage I/O (V) 1.8V or 3.3 V 13 mm x 13 mm, 361-Ball 0.65 mm pitch, PBGA (ZCE) Packages 16 mm x 16 mm, 361-Ball 0.80 mm pitch, PBGA (ZWT) Submit Documentation Feedback Device Overview 9 |
Similar Part No. - TMX320C6748ZCE3 |
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Similar Description - TMX320C6748ZCE3 |
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