1Y

5B

1Z

PRE

3-State_5

5Y

5Z

I2C_EN

I2C

IF

5A

EQ

1B

1A

PRE

2

2

ADDR1

ADDR2

SCL

SDA

RESN

EQ

EQ_5

EQ_1

3-State_1

0Y

0Z

PRE

0B

0A

2

EQ

EQ_0

3-State_0

2Y

2Z

PRE

2B

2A

2

EQ

EQ_2

3-State_2

7B

3-State_7

7Y

7Z

7A

EQ

PRE

2

EQ_7

3B

3-State_3

3Y

3Z

3A

EQ

PRE

2

EQ_3

4B

3-State_4

4Y

4Z

4A

EQ

PRE

2

EQ_4

6B

3-State_6

6Y

6Z

6A

EQ

PRE

2

EQ_6

SN65LVCP418

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

LOGIC DIAGRAM

A.

B.

2

Submit Documentation Feedback

Copyright © 2009, Texas Instruments Incorporated

Product Folder Link(s): SN65LVCP418