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TSB12LV23PZ Datasheet(PDF) 5 Page - Texas Instruments |
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TSB12LV23PZ Datasheet(HTML) 5 Page - Texas Instruments |
5 / 85 page v 7.2 Recommended Operating Conditions 7–2 . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3 Electrical Characteristics Over Recommended Operating Conditions 7–3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4 Switching Characteristics for PCI Interface 7–3 . . . . . . . . . . . . . . . . . . . . . . 7.5 Switching Characteristics for PHY-Link Interface 7–3 . . . . . . . . . . . . . . . . . 8 Mechanical Information 8–1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . List of Illustrations Figure Title Page 2–1 Terminal Assignments 2–1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1 TSB12LV23 Block Diagram 3–2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1 GPIO2 and GPIO3 5–1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . List of Tables Table Title Page 2–1 Signals Sorted by Pin Number 2–2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2 Power Supply 2–2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3 PCI System 2–3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4 PCI Address and Data 2–3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5 PCI Interface Control 2–4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6 IEEE1394 PHY/Link 2–4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7 Miscellaneous 2–5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1 Bit Field Access Tag Descriptions 3–1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2 PCI Configuration Register Map 3–3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3 PCI Command Register Description 3–4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4 PCI Status Register Description 3–5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5 Class Code and Revision ID Register Description 3–6 . . . . . . . . . . . . . . . . . . . . . 3–6 Latency Timer and Class Cache Line Size Register Description 3–6 . . . . . . . . . 3–7 Header Type and BIST Register Description 3–7 . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8 OHCI Base Address Register Description 3–7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9 CIS Base Address Register Description 3–8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10 CardBus CIS Pointer Register Description 3–9 . . . . . . . . . . . . . . . . . . . . . . . . . . 3–11 PCI Subsystem Identification Register Description 3–9 . . . . . . . . . . . . . . . . . . . . 3–12 Interrupt Line and Pin Registers Description 3–10 . . . . . . . . . . . . . . . . . . . . . . . . . 3–13 MIN_GNT and MAX_LAT Register Description 3–11 . . . . . . . . . . . . . . . . . . . . . . . 3–14 PCI OHCI Control Register Description 3–11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15 Capability ID and Next Item Pointer Registers Description 3–12 . . . . . . . . . . . . . 3–16 Power Management Capabilities Register Description 3–13 . . . . . . . . . . . . . . . . 3–17 Power Management Control and Status Register Description 3–14 . . . . . . . . . . 3–18 Power Management Extension Registers Description 3–14 . . . . . . . . . . . . . . . . . |
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