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ADS1248IPWR Datasheet(PDF) 9 Page - Texas Instruments |
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ADS1248IPWR Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 60 page  TIMING DIAGRAMS SCLK DOUT[7] DOUT[6] DOUT[5] DOUT[4] DOUT[1] DOUT[0] DIN[0] DIN[7] DIN[6] DIN[5] DIN[4] DIN[1] DIN[0] CS DOUT/DRDY (1) DIN t CSSC t DIST t DIHD t SCLK t SCCS t CSDO t DOPD t SPWL t SPWH t DOHD SCLK (3) 1 2 3 8 7 6 5 4 DRDY t STD t DTS t PWH ADS1246 ADS1247 ADS1248 www.ti.com .................................................................................................................................................. SBAS426C – AUGUST 2008 – REVISED AUGUST 2009 Figure 1. Serial Interface Timing Table 1. Timing Characteristics for Figure 1(1) SYMBOL DESCRIPTION MIN MAX UNIT tCSSC CS low to first SCLK high (set up time) 10 ns tSCCS SCLK low to CS high (hold time) 7 tOSC (2) tDIST DIN set up time 5 ns tDIHD DIN hold time 5 ns tDOPD SCLK rising edge to new data valid 30 ns tDOHD DOUT hold time 0 ns 500 ns tSCLK SCLK period 64 Conversions tSPWH SCLK pulse width high 0.25 0.75 tSCLK tSPWL SCLK pulse width low 0.25 0.75 tSCLK tCSDO CS high to DOUT high impedance 10 ns (1) DRDY MODE bit = 0. (2) tOSC = 1/fCLK. The default clock frequency fCLK = 4.096MHz. Figure 2. SPI Interface Timing to Allow Conversion Result Loading(3)(4) Table 2. Timing Characteristics for Figure 2 SYMBOL DESCRIPTION MIN MAX UNIT tPWH DRDY pulse width high 3 tOSC tSTD SCLK low prior to DRDY low 5 tOSC tDTS DRDY falling edge to SCLK rising edge 30 ns (3) This timing diagram is applicable only when the CS pin is low. SCLK need not be low during tSTD when CS is high. (4) SCLK should only be sent in multiples of eight during partial retrieval of output data. Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Link(s): ADS1246 ADS1247 ADS1248 |
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