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ADS1113IDGSR Datasheet(PDF) 19 Page - Texas Instruments |
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ADS1113IDGSR Datasheet(HTML) 19 Page - Texas Instruments |
19 / 34 page ADS1113 ADS1114 ADS1115 www.ti.com ......................................................................................................................................................... SBAS444A – MAY 2009 – REVISED AUGUST 2009 Bits [14:12] MUX[2:0]: Input multiplexer configuration (ADS1115 only) These bits configure the input multiplexer. They serve no function on the ADS1113/4. 000 : AINP = AIN0 and AINN = AIN1 (default) 100 : AINP = AIN0 and AINN = GND 001 : AINP = AIN0 and AINN = AIN3 101 : AINP = AIN1 and AINN = GND 010 : AINP = AIN1 and AINN = AIN3 110 : AINP = AIN2 and AINN = GND 011 : AINP = AIN2 and AINN = AIN3 111 : AINP = AIN3 and AINN = GND Bits [11:9] PGA[2:0]: Programmable gain amplifier configuration (ADS1114 and ADS1115 only) These bits configure the programmable gain amplifier. They serve no function on the ADS1113. 000 : FS = ±6.144V (1) 100 : FS = ±0.512V 001 : FS = ±4.096V (1) 101 : FS = ±0.256V 010 : FS = ±2.048V (default) 110 : FS = ±0.256V 011 : FS = ±1.024V 111 : FS = ±0.256V Bit [8] MODE: Device operating mode This bit controls the current operational mode of the ADS1113/4/5. 0 : Continuous conversion mode 1 : Power-down single-shot mode (default) Bits [7:5] DR[2:0]: Data rate These bits control the data rate setting. 000 : 8SPS 100 : 128SPS (default) 001 : 16SPS 101 : 250SPS 010 : 32SPS 110 : 475SPS 011 : 64SPS 111 : 860SPS Bit [4] COMP_MODE: Comparator mode (ADS1114 and ADS1115 only) This bit controls the comparator mode of operation. It changes whether the comparator is implemented as a traditional comparator (COMP_MODE = '0') or as a window comparator (COMP_MODE = '1'). It serves no function on the ADS1113. 0 : Traditional comparator with hysteresis (default) 1 : Window comparator Bit [3] COMP_POL: Comparator polarity (ADS1114 and ADS1115 only) This bit controls the polarity of the ALERT/RDY pin. When COMP_POL = '0' the comparator output is active low. When COMP_POL='1' the ALERT/RDY pin is active high. It serves no function on the ADS1113. 0 : Active low (default) 1 : Active high Bit [2] COMP_LAT: Latching comparator (ADS1114 and ADS1115 only) This bit controls whether the ALERT/RDY pin latches once asserted or clears once conversions are within the margin of the upper and lower threshold values. When COMP_LAT = '0', the ALERT/RDY pin does not latch when asserted. When COMP_LAT = '1', the asserted ALERT/RDY pin remains latched until conversion data are read by the master or an appropriate SMBus alert response is sent by the master, the device responds with its address, and it is the lowest address currently asserting the ALERT/RDY bus line. This bit serves no function on the ADS1113. 0 : Non-latching comparator (default) 1 : Latching comparator Bits [1:0] COMP_QUE: Comparator queue and disable (ADS1114 and ADS1115 only) These bits perform two functions. When set to '11', they disable the comparator function and put the ALERT/RDY pin into a high state. When set to any other value, they control the number of successive conversions exceeding the upper or lower thresholds required before asserting the ALERT/RDY pin. They serve no function on the ADS1113. 00 : Assert after one conversion 01 : Assert after two conversions 10 : Assert after four conversions 11 : Disable comparator (default) (1) This parameter expresses the full-scale range of the ADC scaling. In no event should more than VDD + 0.3V be applied to this device. Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 19 Product Folder Link(s): ADS1113 ADS1114 ADS1115 |
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