www.ti.com ......................................................................................................................................................... SBAS444A – MAY 2009 – REVISED AUGUST 2009
When the master has finished communicating with a
byte; the I2C specification prohibits acknowledgment
slave, it may issue a STOP condition. When a STOP
of the Hs master code. Upon receiving a master
condition is issued, the bus becomes idle again. The
code, the ADS1113/4/5 switch on Hs mode filters,
master may also issue another START condition.
and communicate at up to 3.4MHz. The ADS1113/4/5
When a START condition is issued while the bus is
switch out of Hs mode with the next STOP condition.
active, it is called a repeated START condition.
For more information on high-speed mode, consult
See the Timing Requirements section for a timing
the I2C specification.
diagram showing the ADS1113/4/5 I2C transaction.
SLAVE MODE OPERATIONS
2C ADDRESS SELECTION
The ADS1113/4/5 can act as either slave receivers or
The ADS1113/4/5 have one address pin, ADDR, that
sets the I2C address. This pin can be connected to
ADS1113/4/5 cannot drive the SCL line.
ground, VDD, SDA, or SCL, allowing four addresses
to be selected with one pin as shown in Table 5 .
The state of the address pin ADDR is sampled
In slave receive mode the first byte transmitted from
the master to the slave is the address with the R/W
bit low. This byte allows the slave to be written to.
Table 5. ADDR Pin Connection and
The next byte transmitted by the master is the
Corresponding Slave Address
acknowledge receipt of the register pointer byte. The
next two bytes are written to the address given by the
register pointer. The ADS1113/4/5 acknowledge each
byte sent. Register bytes are sent with the most
significant byte first, followed by the least significant
2C GENERAL CALL
The ADS1113/4/5 respond to the I2C general call
In slave transmit mode, the first byte transmitted by
address (0000000) if the eighth bit is '0'. The devices
the master is the 7-bit slave address followed by the
acknowledge the general call address and respond to
high R/W bit. This byte places the slave into transmit
commands in the second byte. If the second byte is
mode and indicates that the ADS1113/4/5 are being
00000110 (06h), the ADS1113/4/5 reset the internal
read from. The next byte transmitted by the slave is
registers and enter power-down mode.
the most significant byte of the register that is
indicated by the register pointer. This byte is followed
2C SPEED MODES
remaining least significant byte is then sent by the
The I2C bus operates at one of three speeds.
slave and is followed by an acknowledgment from the
Standard mode allows a clock frequency of up to
master. The master may terminate transmission after
100kHz; fast mode permits a clock frequency of up to
any byte by not acknowledging or issuing a START or
400kHz; and high-speed mode (also called Hs mode)
allows a clock frequency of up to 3.4MHz. The
ADS1113/4/5 are fully compatible with all three
WRITING/READING THE REGISTERS
To access a specific register from the ADS1113/4/5,
No special action is required to use the ADS1113/4/5
the master must first write an appropriate value to the
in standard or fast mode, but high-speed mode must
Pointer register. The Pointer register is written directly
be activated. To activate high-speed mode, send a
after the slave address byte, low R/W bit, and a
special address byte of 00001xxx following the
successful slave acknowledgment. After the Pointer
START condition, where xxx are bits unique to the
register is written, the slave acknowledges and the
Hs-capable master. This byte is called the Hs master
master issues a STOP or a repeated START
code. (Note that this is different from normal address
bytes; the eighth bit does not indicate read/write