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ADS62P49 Datasheet(PDF) 20 Page - Texas Instruments

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Part No. ADS62P49
Description  Dual Channel 14-/12-Bit, 250-/210-MSPS ADC With DDR LVDS and Parallel CMOS Outputs
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

ADS62P49 Datasheet(HTML) 20 Page - Texas Instruments

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SERIAL REGISTER MAP
ADS62P49 / ADS62P29
ADS62P48 / ADS62P28
SLAS635A – APRIL 2009 – REVISED JUNE 2009............................................................................................................................................................. www.ti.com
Table 7. Summary of Functions Supported by Serial Interface (1)
REGISTER
REGISTER FUNCTIONS
ADDRESS
A7–A0
D7
D6
D5
D4
D3
D2
D1
D0
IN HEX
00
<RESET>
0
0
0
0
0
0
<SERIAL
Software Reset
READOUT>
20
0
0
0
0
0
<ENABLE
0
0
LOW
SPEED
MODE>
3F
0
<REF>
0
0
0
0
<STANDBY>
0
Internal or external reference
40
0
0
0
0
<POWER DOWN MODES>
41
<LVDS CMOS>
0
0
0
0
0
0
0
Output interface
44
<CLKOUT EDGE CONTROL>
0
0
50
0
<ENABLE INDIVIDUAL
0
0
0
<DATA FORMAT>
0
CHANNEL CONTROL>
2s comp or offset binary
51
<CUSTOM PATTERN LOW>
52
0
0
<CUSTOM PATTERN HIGH>
53
0
<ENABLE OFFSET
0
CORRECTION – CH A>
55
<GAIN PROGRAMMABILITY – CH A>
<OFFSET CORRECTION TIME
0 to 6 dB in 0.5 dB steps
CONSTANT – CH A>
57
0
<FINE GAIN ADJUST – CH A>
+0.001 dB to +0.134 dB, in 128 steps
62
0
0
0
0
0
<TEST PATTERNS – CH A>
63
0
0
<OFFSET PEDESTAL – CH A>
66
0
<ENABLE OFFSET
0
0
0
0
0
0
CORRECTION – CH B>
68
<GAIN PROGRAMMABILITY – CH B>
<OFFSET CORRECTION TIME
0 to 6 dB in 0.5 dB steps
CONSTANT – CH B>
6A
0
<FINE GAIN ADJUST – CH B>
+0.001 dB to +0.134 dB, in 128 steps
75
0
0
0
0
0
<TEST PATTERNS – CH B>
76
0
0
<OFFSET PEDESTAL – CH B>
(1)
Multiple functions in a register can be programmed in a single write operation.
20
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Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28


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